tag:blogger.com,1999:blog-54881325728645850982024-03-06T03:02:01.397-05:00Chipworks Real ChipsDick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.comBlogger51125tag:blogger.com,1999:blog-5488132572864585098.post-27332035529880077092016-01-14T15:42:00.000-05:002016-01-14T15:42:48.429-05:00What to Expect in 2016 in the Chipworld<div style="clear: both; text-align: left;">
It’s the time in the media world that we see a frenzy of predictions for the coming year. They are mostly business or tech trends, so I figured I might as well chip in (har! har!), and give a more detailed idea of what new semiconductor products we look forward to this year, now that we are in 2016.</div>
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This might seem to be a bit like fortune-telling, but it’s actually a compilation of the notes we’ve made from this year’s press announcements, coupled with the trends we’ve observed in our reverse engineering, and keeping an open ear at the industry events that we’ve attended. <br />
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<h3>
Logic and Foundries</h3>
2016 will be a relatively quiet year when it comes to the leading-edge processes, since we do not expect to see a high-volume of 10 nm products this year. There has been a fair bit of comment that the upcoming Apple A10 processor might be on 10 nm this autumn, but to me it seems a real stretch to expect a full node advance barely 18 months after the introduction of a 14 nm product from Samsung, and a 16 nm product from TSMC, especially in the volume that Apple would require.<br />
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We do expect to see the second generation 14/16 nm processes, FinFET Plus (16FF+) from TSMC and 14LPP from Samsung and possibly their co-supplier GLOBALFOUNDRIES. The second-tier foundries such as UMC and SMIC will be ramping up their 28 nm high-k metal gate (HKMG) product, so we will be monitoring those as we get them. It appears that UMC will be skipping 20 nm and going straight to 14 nm, but that will not likely appear until 2017.<br />
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When it comes to fully depleted silicon on insulator (FD-SOI), we expect to see a mainstream 28 nm product this year, since Samsung has stated that they are producing, and <a href="http://www.advancedsubstratenews.com/2015/12/yes-28nm-fd-soi-silicon-is-running-samsung-interview-part-1-of-3/" target="_blank">have shipped more than a million wafers</a>, with STMicroelectronics as one of their lead customers. Chipworks has already analyzed <a href="https://chipworks.secure.force.com/catalog/ProductDetails?sku=SFA-SF3301-FC481&viewState=DetailView&cartID=&g=" target="_blank">a custom 28 nm FD-SOI ASIC</a> manufactured at STMicroelectronics, which was a simple implementation without back-bias. For the mainstream parts, we will be analyzing back-bias implementation, if found, as it is touted as one of the big advantages of FD-SOI.<br />
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GLOBALFOUNDRIES is also on the FD-SOI bandwagon, but they seem to be concentrating on their 22FDX™ processes. A number of the ASIC design houses are claiming to be designing into those, so with luck we will see some very early product by year-end.<br />
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There will also be a continued emphasis on low power variants of older generation processes, such as 40 and 55 nm, aimed at mobile/wearable devices where battery life is critical.<br />
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To finish up, another process sector where we expect to see development is radio frequency silicon on insulator (RF-SOI). We are already seeing the introduction of RF-SOI into products such as antenna switches for the RF front end of mobile phones.<br />
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<h3>
DRAM</h3>
This will be another year of evolution for dynamic random-access memory (DRAM), with the introduction of 1X nm generation memories by the big three (Micron, Samsung, and SK Hynix), although possibly not until year-end.<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgW0ntLxQJjKjMXcyGDXUpD_76F9Affc22HO-FVWPGTGemfEGbfY4MRTEdaSj3s-MQ1QJnzIppr5NfKVgBRg8t_d70mJqGkpN43WklS1kUBUjolO_5DtI-mu2KjlqNxedBQ38gvFjVA3Gy4/s1600/Micron.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="88" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgW0ntLxQJjKjMXcyGDXUpD_76F9Affc22HO-FVWPGTGemfEGbfY4MRTEdaSj3s-MQ1QJnzIppr5NfKVgBRg8t_d70mJqGkpN43WklS1kUBUjolO_5DtI-mu2KjlqNxedBQ38gvFjVA3Gy4/s320/Micron.png" width="320" /></a></div>
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Micron has 1X and 1Y nm nodes in its roadmap (above), enabling 1X volume mid-2016.<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjG1oh2PeDt-LwVE-uQbB_ihriIHuPWm5LhN7JaUXQ-ZKd6n1nkNgNv3mdNaU9QuEfpGHTgBJKxKANYhyphenhyphenws4gZ7BtpMEbUmnpEG_pL2PYlFQgo_JD1Bf9Yz7ixC9yriNE9cIA3RDBiehGD2/s1600/Samsung.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="128" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjG1oh2PeDt-LwVE-uQbB_ihriIHuPWm5LhN7JaUXQ-ZKd6n1nkNgNv3mdNaU9QuEfpGHTgBJKxKANYhyphenhyphenws4gZ7BtpMEbUmnpEG_pL2PYlFQgo_JD1Bf9Yz7ixC9yriNE9cIA3RDBiehGD2/s320/Samsung.png" width="320" /></a></div>
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Samsung predicts three 1X nm nodes (see above), though there is no time scale here; however, we already have their <a href="https://chipworks.secure.force.com/catalog/ProductDetails?sku=SAM-K4B4G0846E-BCK0&viewState=DetailView&cartID=&g=" target="_blank">20 nm part</a>, which is in volume production, so it’s reasonable to expect a 1X nm part this year. We haven’t heard anything formal from SK Hynix, but again, we already have their <a href="https://chipworks.secure.force.com/catalog/ProductDetails?sku=HYN-H9HKNNNBTUMU-BRNLH&viewState=DetailView&cartID=&g=" target="_blank">20 nm part</a>, so we would expect a 1X nm device in 2016. <br />
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<a href="https://www.blogger.com/" imageanchor="1" style="clear: right; float: right; margin-bottom: 1em; margin-left: 1em;"></a>The other facet of the DRAM business is stacked memory using through-silicon vias (TSVs); in 2015 we saw the <a href="https://chipworks.secure.force.com/catalog/ProductDetails?sku=SAM-K4AAG045WD-4CRB&viewState=DetailView&cartID=&g=" target="_blank">Samsung version</a>, and the <a href="https://chipworks.secure.force.com/catalog/ProductDetails?sku=AMD-215-0862040&viewState=DetailView&cartID=&g=" target="_blank">SK Hynix High Bandwidth Memory</a> (HBM). We’re still waiting for the Intel/Micron Hybrid Memory Cube (HMC), and we expect to get our hands on that this year, as well as the <a href="https://www.skhynix.com/eng/product/dramHBM.jsp" target="_blank">HBM2</a> from SK Hynix.<br />
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<h3>
NAND Flash</h3>
<a href="https://www.blogger.com/" imageanchor="1" style="clear: right; float: right; margin-bottom: 1em; margin-left: 1em;"></a>The big news in NAND flash memory is the introduction of 3D/vertical technology, with the bitcells stacked one above another instead of on the die surface. Samsung launched their V-NAND over a year ago, with 32 active layers in both multi-level cell (MLC) and tri-level cell (TLC) versions, using charge-trap storage technology. They are now shipping the third generation part (256 Gb) with 48 layers, so we should see that in the near future.<br />
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<a href="https://www.blogger.com/" imageanchor="1" style="clear: right; float: right; margin-bottom: 1em; margin-left: 1em;"></a>Last month, at <a href="http://ieee-iedm.org/" target="_blank">IEDM</a> (International Electron Devices Meeting), Intel/Micron <a href="http://electroiq.com/chipworks_real_chips_blog/2015/12/10/intelmicron-detail-their-3d-nand-at-iedm/" target="_blank">detailed their 3D-NAND</a>, a 32-layer device, this time using conventional floating gate charge storage. According to their investor calls, they are sampling these at the moment and should be shipping volume in the second half of this year.<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh7T9DIH3O6B6XYBCvMgPh1gCoIfTqZNm1pJao64G0YLBE4j97Z1CYNU-PwcVJOQDcRA3h9GyXeecKsZRHUQK9Km8dv11KDp83j1t86JlLhIdbx4E52yoF12ZrCVCgWAZ-TIl_ierHHcdgn/s1600/3D-NAND5-a-ann.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="141" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh7T9DIH3O6B6XYBCvMgPh1gCoIfTqZNm1pJao64G0YLBE4j97Z1CYNU-PwcVJOQDcRA3h9GyXeecKsZRHUQK9Km8dv11KDp83j1t86JlLhIdbx4E52yoF12ZrCVCgWAZ-TIl_ierHHcdgn/s320/3D-NAND5-a-ann.png" width="320" /></a></div>
<div style="text-align: center;">
SEM cross-section of Intel/Micron vertical-channel 3D-NAND structure</div>
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SanDisk/Toshiba are also sampling, but their 3D-NAND is a 48-layer, 256-Gb TLC device, built using their own Bit-Cost Scalable (BiCS) charge-trap technology. They have been more cautious about the economics of launching 3D technology, but again I look forward to getting some in 2016. Last, but not necessarily least, SK Hynix claim that they are already in 3D production, and we should also see their floating-gate version this year.<br />
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<a href="https://www.blogger.com/" imageanchor="1" style="clear: right; float: right; margin-bottom: 1em; margin-left: 1em;"></a>In parallel, all the companies are still evolving planar flash products – we will likely find 13 – 15 nm planar flash chips being launched, since the 15/16-nm ones are already here.<br />
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<h3>
Emerging Memory
</h3>
The highest-profile announcement this year for this memory class was from Intel/Micron, on their 3D XPoint memory; this appears to be some sort of resistive random-access memory (RRAM), using “bulk properties” to provide memory storage in a cross-point layout. <br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgmfJG9TqDPdg63ttJYWUnOmamstMwyi63UV6Fkg9rC8eTFe-HWZU0_bLweIne0myZTHtICD5cJPflHlkuJTN6BBFjrd2YG6bPqPxv6j1osEfgg51Diwg6JX30GXYaKcAQKPfgJDfy3ski5/s1600/Fig-4%255B1%255D.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="172" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgmfJG9TqDPdg63ttJYWUnOmamstMwyi63UV6Fkg9rC8eTFe-HWZU0_bLweIne0myZTHtICD5cJPflHlkuJTN6BBFjrd2YG6bPqPxv6j1osEfgg51Diwg6JX30GXYaKcAQKPfgJDfy3ski5/s320/Fig-4%255B1%255D.png" width="320" /></a></div>
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Both Intel and Micron predict a big future for this product; Micron claims that the <a href="https://www.micron.com/about/emerging-technologies/3d-xpoint-technology" target="_blank">3D XPoint</a> business could easily be of the same order of magnitude as their DRAM businesses by 2018, and Intel sees broad applications for 3D XPoint memory (dubbed <a href="http://www.anandtech.com/show/9541/intel-announces-optane-storage-brand-for-3d-xpoint-products" target="_blank">Optane</a>), and says that it will be available this year for PC and server usage. <br />
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Less noticed was a similar release from <a href="https://www.sandisk.com/about/media-center/press-releases/2015/sandisk-and-hp-launch-partnership" target="_blank">SanDisk</a> and <a href="http://www8.hp.com/ca/en/hp-news/press-release.html?id=2099577#.VoqTaJ0o5LM" target="_blank">HP</a>, also detailing storage-class RRAM-based memory, but with no details as to launch dates. Micron and Sony also have a jointly developed RRAM, but again no dates. <br />
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<h3>
Image Sensors
</h3>
<div style="text-align: left;">
There has been a steady evolution in the image sensor biz, with Sony leading the pack, and culminating in the deep-trench isolation between pixels in the Apple 6s/6s Plus camera. Sony has had a two year+ lead in stacking the sensor on top of the image processor and connecting the two with custom TSVs, but we now see OmniVision and Samsung with design wins using multiple versions of its new stacked chip products.</div>
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We can, no doubt, expect to see a further-evolved camera chip in the iPhone 7, and Apple’s competitors will also be pushing the envelope, so we will be monitoring every new smartphone to see what appears.
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<br />
Meanwhile, other sectors are developing fast – to name two, the push on automated driver self-assist (ADAS) and self-driving vehicles is providing a new space for lower-tech (but different specifications) image sensors, and security is likely to be a hot market given last year’s terror attacks.
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<h3 style="text-align: left;">
Advanced Packaging </h3>
<div style="text-align: left;">
Packaging technology has been in as much ferment as any of the wafer fab technologies, with 2.5/3D stacking getting most of the press. We expect 2016 to be a busy year in that space too; TSMC is producing its <a href="http://www.tsmc.com/english/dedicatedFoundry/services/cowos.htm" target="_blank">Chip-on-Wafer-on-Substrate</a> (CoWoS) silicon interposer for a limited range of products, and seems about to launch its cheaper integrated fan-out (InFO) organic substrate, possibly using it for the Apple A10 system-on-chip (SoC) this fall.<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhTLf8ubli0e1Sfa_1mLTjHZMQfeiaBeK_IC1JUATJB0bAioHQl3pYmp2QXrjiSqXUjLEVdtdYEcSfbzwWd89VBQOlYyS1EPzdjtNUiolTKpwZm9VD40Ep9Es2Qm0hH5pMBw9Kkn5yy1ZVr/s1600/Fig-5%255B1%255D.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="229" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhTLf8ubli0e1Sfa_1mLTjHZMQfeiaBeK_IC1JUATJB0bAioHQl3pYmp2QXrjiSqXUjLEVdtdYEcSfbzwWd89VBQOlYyS1EPzdjtNUiolTKpwZm9VD40Ep9Es2Qm0hH5pMBw9Kkn5yy1ZVr/s320/Fig-5%255B1%255D.png" width="320" /></a></div>
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TSMC has TSVs in volume production, though not high-density for 2.5/3D; the <a href="https://chipworks.secure.force.com/catalog/ProductDetails?sku=APP-MKQK2VCA_Fingerprint-Sensor&viewState=DetailView&cartID=&g=" target="_blank">new fingerprint sensor in the Apple 6s/6s Plus</a> uses TSVs so that the wire bonds don’t get in the way of the sapphire touchpad.</div>
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<div style="text-align: left;">
Intel has a parallel “<a href="http://www.intel.com/content/www/us/en/foundry/emib.html" target="_blank">Embedded Multi-die Interconnect Bridge</a>” (EMIB) technology (to TSMC’s InFO), and given the completed Altera deal, we may finally see a 14 nm field-programmable gate array (FPGA) product with EMIB this year.</div>
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Add in the Intel/Micron HMC, SK Hynix’s HBM2 and Wide IO2 stack, and the OSATs are also pushing the envelope and likely to ship new formats this year, so there will be plenty for us to look at.</div>
<h3>
Wrap-up</h3>
This has been a relatively high-level review of what we expect this year, but as you can see from the above, it will be quite a hectic year – lots of new technology for us to analyze!<br />
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Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com2tag:blogger.com,1999:blog-5488132572864585098.post-65673780607922069022016-01-10T12:56:00.000-05:002016-01-10T12:59:35.512-05:00Intel/Micron Detail Their 3D-NAND at IEDM<br />
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<span lang="EN-US" style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-US;">On
the Monday afternoon at </span><a href="http://ieee-iedm.org/"><span lang="EN-US" style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-US;"><span style="color: blue;">IEDM</span></span></a><span lang="EN-US" style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-US;">
the key paper for me was the Intel/Micron talk on their 3D-NAND flash part
(paper 3.3), which is currently sampling to customers. Samsung put their V-NAND
flash on the market last year, but that uses charge-trap technology, whereas
the Intel/Micron device has adapted conventional floating gate technology to
the vertical direction.</span></div>
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<span lang="EN-US" style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-US;"><span lang="EN-US" style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">This is the first-generation product, with 32
active tiers plus additional layers for dummy wordlines and source and drain
select gates. A vertical channel surround-gate structure is used for the flash
cells. The CMOS decoders and sense-amps are situated under the NAND flash array,
which saves significantly on die area. It appears that this product will be a
256-Gb memory, or 384 Gb when the TLC version is introduced. Die size is 168.5
mm<sup>2</sup>, giving a bit density of 1.52 and 2.28 Gb/mm<sup>2</sup> for the
MLC and TLC devices.</span><o:p></o:p></span></div>
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<div style="text-align: center;">
<span lang="EN-US" style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-US;">Intel/Micron 3D-NAND flash die (Source:
Intel/Micron/IEDM)<o:p></o:p></span></div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiSsjSz7QSqUo_nODkiN6_omShQEAtDJwt5my_SRYjQDWUMLsyt99e-nbsbYX6HKLLSWySN-lmKya_39efQvklbk3EdfHFL2js4umeIMfPKiuOx1w-9TGRrX3JwQuuxa-2ka3vd5UDw2JCX/s1600/3D-NAND01.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="232" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiSsjSz7QSqUo_nODkiN6_omShQEAtDJwt5my_SRYjQDWUMLsyt99e-nbsbYX6HKLLSWySN-lmKya_39efQvklbk3EdfHFL2js4umeIMfPKiuOx1w-9TGRrX3JwQuuxa-2ka3vd5UDw2JCX/s320/3D-NAND01.png" width="320" /></a></div>
<span lang="EN-US" style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-US;"><o:p><span lang="EN-US" style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">The wordlines/control gates are horizontal
polysilicon layers with an ONO inter-poly dielectric, and the floating gates
are also polySi. The vertical channel and tunnel dielectric are formed in holes
etched through a horizontal polySi/oxide stack.</span> </o:p></span><br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhY84UyTbc_v-Unghz_erGfBll1hKTHLU-Zz1gt2NhU_c867ZCS9lHzVU1A-bQuxzYCKDyNRJcmeHg_NiQV7oX7NfK9qHyHtnZbs6mlIsmHW4uSmcfRW43c1LnY04KKGtmfeJfehmq9WXNv/s1600/3D-NAND5-a-ann.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="141" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhY84UyTbc_v-Unghz_erGfBll1hKTHLU-Zz1gt2NhU_c867ZCS9lHzVU1A-bQuxzYCKDyNRJcmeHg_NiQV7oX7NfK9qHyHtnZbs6mlIsmHW4uSmcfRW43c1LnY04KKGtmfeJfehmq9WXNv/s320/3D-NAND5-a-ann.png" width="320" /></a></div>
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<span lang="EN-US" style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-US;">SEM cross-section of vertical-channel 3D-NAND
structure<span style="mso-spacerun: yes;"> </span>(Source: Intel/Micron/IEDM)<o:p></o:p></span></div>
<br />
<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;">The process is shown
below; the cell hole is first etched through the wordline tiers, and then the
control gate is recessed back and the inter-poly dielectric is formed. The
floating gate is then deposited, and etched back to form an isolated floating
gate in each cell; the tunnel-oxide is formed, and the polySi channel is
deposited to line the hole in the stack. <o:p></o:p></span><br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEicY3wRSg5eyecMpq4uKpCKnvYpakUOm6qwciysxqd4Zy_DVgo3xa2tn_DReixRNAJNCo58nOkErJCQ_MZ9NX-ZygMFs9bGtuHzG-srmJTFQsdc1edQkouK9oIMS7lqgyN9ATmcJ74iVL4z/s1600/3D-NAND3.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEicY3wRSg5eyecMpq4uKpCKnvYpakUOm6qwciysxqd4Zy_DVgo3xa2tn_DReixRNAJNCo58nOkErJCQ_MZ9NX-ZygMFs9bGtuHzG-srmJTFQsdc1edQkouK9oIMS7lqgyN9ATmcJ74iVL4z/s320/3D-NAND3.png" width="319" /></a></div>
<div style="text-align: center;">
<span lang="EN-US" style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-US;">Process flow of vertical-channel 3D-NAND stack
formation<span style="mso-spacerun: yes;"> </span>(Source: Intel/Micron/IEDM)</span><o:wrapblock></o:wrapblock></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;">An image of the full
stack is shown below; I see 38 wordline layers, plus a thick polySi layer at
top and bottom of the stack, presumably for the drain and source select
transistors. There are two tungsten metal layers below the stack for the decoders
and sense-amps, and also the wordline drivers; and it looks like the M3 bitline
is also tungsten. There is another metal level above used for power busses and
global interconnects, but we don’t know if that is copper or aluminum.<o:p></o:p></span></div>
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<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;">Putting the wordline
drivers under the array is claimed to keep the wordlines short, but it raises
some questions – how are the wordlines contacted from below? Do we have the
sort of staircase at the ends of the wordlines that </span><a href="http://electroiq.com/chipworks_real_chips_blog/2014/08/"><span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;"><span style="color: blue;">we
saw in the Samsung V-NAND</span></span></a><span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;">, and could it be inverted? (Can’t
imagine that!)<o:p></o:p></span></div>
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjCxj4KLzzsj06ZvzXI_GdhUdegz51YEtgmk6LhWUPrEhRKOR-h08Atu1VOhHqeLclNuunLBg97t46_04l5Zm-Cl02En_QPnjBFna9Wz6MHFHwgqJemSkcpu0oUkjG7Xm7IGfa2twTlI11r/s1600/3D-NAND6-a-ann.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjCxj4KLzzsj06ZvzXI_GdhUdegz51YEtgmk6LhWUPrEhRKOR-h08Atu1VOhHqeLclNuunLBg97t46_04l5Zm-Cl02En_QPnjBFna9Wz6MHFHwgqJemSkcpu0oUkjG7Xm7IGfa2twTlI11r/s320/3D-NAND6-a-ann.png" width="68" /></a></div>
<div align="center" class="MsoNormal" style="margin: 6pt 0in 0pt; text-align: center;">
<span lang="EN-US" style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-US;">SEM cross-section of 3D-NAND stack<span style="mso-spacerun: yes;"> </span>(Source: Intel/Micron/IEDM)</span></div>
<o:wrapblock></o:wrapblock><div align="center" class="MsoNormal" style="margin: 6pt 0in 0pt; text-align: center;">
<br /></div>
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<b><span lang="EN-US" style="color: yellow; font-family: "Arial","sans-serif"; font-size: 20pt; mso-ansi-language: EN-US; mso-font-kerning: 12.0pt;">NAND cell
stack</span></b><o:p></o:p></div>
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<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;"><o:p></o:p></span></span></div>
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<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-CA; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">The vertical channels contact what looks like a
polySi sourceline at the base of the stack; it’s a bit clearer in this
schematic:</span></div>
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiVk7oJGrQpge4ozyms7G4oiRc8gWb9quptnNUlQLl1CX6tnpbYhh46cABYNNW-Bs0Y-rlxKhrNWFuiHvzuJW3kMUT0_WAnP7SNykFzV1V2vabdojkUEZ7sq4lcKY9cSBtsXnfhyFM7aEDz/s1600/3D-NAND7-ann.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiVk7oJGrQpge4ozyms7G4oiRc8gWb9quptnNUlQLl1CX6tnpbYhh46cABYNNW-Bs0Y-rlxKhrNWFuiHvzuJW3kMUT0_WAnP7SNykFzV1V2vabdojkUEZ7sq4lcKY9cSBtsXnfhyFM7aEDz/s320/3D-NAND7-ann.png" width="253" /></a></div>
<div align="center" class="MsoNormal" style="margin: 6pt 0in 0pt; text-align: center;">
<span lang="EN-US" style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-US;">Schematic of base of 3D-NAND stack<span style="mso-spacerun: yes;"> </span>(Source: Intel/Micron/IEDM)</span><span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;"><o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;">While the NAND cells
are floating gate cells, we can see that the source and drain select devices
are single gate oxide transistors.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;">The larger size of the
cell improves the performance since it has a higher cell capacitance – more
electrons can be stored, and a better natural Vt distribution (~50%) is
achieved. (Note that at 20-nm planar, less than 10 electrons gave 100mv Vt
shift!)</span><br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEioZw_6NwyNDfxCPtO3BCw6kjHMXjH-BwpCzZtu9hYOQgRvFgTTozUxcRM_5Wgrh7RyYMswpAugCNa2L7TF5x2oaWyRFOpMzB24drLzck2yNpERMGtzejIXacp5K1MqrxZgBCfHHUiOFZsn/s1600/3D-NAND10.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="136" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEioZw_6NwyNDfxCPtO3BCw6kjHMXjH-BwpCzZtu9hYOQgRvFgTTozUxcRM_5Wgrh7RyYMswpAugCNa2L7TF5x2oaWyRFOpMzB24drLzck2yNpERMGtzejIXacp5K1MqrxZgBCfHHUiOFZsn/s320/3D-NAND10.png" width="320" /></a></div>
<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;"><o:p></o:p></span> </div>
<div style="text-align: center;">
<span lang="EN-US" style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-US;">Cell/cell interference of 3D-NAND vs planar NAND<span style="mso-spacerun: yes;"> </span>(Source: Intel/Micron/IEDM)</span><span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;"><o:p></o:p></span></div>
<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-CA; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;"></span><br />
<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-CA; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">The cell geometry also means that the cell/cell
interference is reduced – again, comparing to the 20-nm planar chip;</span><br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgrygUMZTiFAj95byXtNJ9722gHciexy7r1j_cYBjfl-NTBBXT3F8bxP6P1PLJrSTOCO7E_bEYaUapUv55aRhN7zbz7w3wLBJj0ftLcArexyCWthq_fKs54PXUMrP9IgJVRi_kXdskcjFVw/s1600/3D-NAND11-ann.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="199" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgrygUMZTiFAj95byXtNJ9722gHciexy7r1j_cYBjfl-NTBBXT3F8bxP6P1PLJrSTOCO7E_bEYaUapUv55aRhN7zbz7w3wLBJj0ftLcArexyCWthq_fKs54PXUMrP9IgJVRi_kXdskcjFVw/s320/3D-NAND11-ann.png" width="320" /></a></div>
<div align="center" class="MsoNormal" style="margin: 6pt 0in 0pt; text-align: center;">
<span lang="EN-US" style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-US;">Cell/cell interference of 3D-NAND vs planar NAND<span style="mso-spacerun: yes;"> </span>(Source: Intel/Micron/IEDM)</span><span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;"><o:p></o:p></span></div>
<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%; mso-ansi-language: EN-CA; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;"></span><br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;">We will see what the
commercial part looks like when we get our hands on one, likely in the first
few months of next year. Unfortunately there are no scale bars on any of the
images, so we have no feel for what the actual dimensions are; though probably
not too different from the Samsung, which is classed as a 40-nm device. <o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;">There are actually not
too many features in common with the Samsung chip – vertical stacking with 32
active layers, and that’s about it. Otherwise, charge-trap technology vs
floating-gate; polySi wordlines vs tungsten; metallization below the stack, vs
none; and maybe a completely different way of accessing the wordlines.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;">For now, we wait and
see!<o:p></o:p></span></div>
<br />
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<span style="font-family: "Times New Roman","serif"; font-size: 12pt; line-height: 115%;"><o:p> </o:p></span></div>
Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-441963598623997812015-08-26T10:13:00.001-04:002015-08-26T10:13:35.217-04:00Apple Watch and ASE Start New Era in SiPBack in April the Apple watch appeared in our labs, and of course we <a href="http://www.chipworks.com/about-chipworks/overview/blog/inside-the-apple-watch-technical-teardown-blog" target="_blank">analyzed it</a> to see its contents. That set us some challenges, since inside the case we have the S1”chip” (as Jony Ive called it in the launch last year). As you can see, it occupies most of the space inside the case, so it’s a pretty large chip; normally only the likes of IBM or Nvidia make chips this large.<br />
<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjcF2eXW0wrwZC0nXb1_MCtkdiz6RdBjGCzwJafsvSNWVP20Y24L8UARslB1lnHwq6OW64mYbcuTnfaCC2NSQbmfdtANxGl4YVDqvkyMqs00Fw8VAtQaqLcRsVk7I82ksc8W2dE5xNDgFiq/s1600/01_1.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjcF2eXW0wrwZC0nXb1_MCtkdiz6RdBjGCzwJafsvSNWVP20Y24L8UARslB1lnHwq6OW64mYbcuTnfaCC2NSQbmfdtANxGl4YVDqvkyMqs00Fw8VAtQaqLcRsVk7I82ksc8W2dE5xNDgFiq/s320/01_1.jpg" width="320" /></a></div>
<br />
Actually, we knew that there had to be multiple chips inside the S1, because we did a <a href="http://www.chipworks.com/about-chipworks/overview/blog/broadcom-wins-wifi-apple-watch" target="_blank">pseudo-teardown last year</a>, based on Apple’s promo video at the time. It turns out that the S1 is actually an assembly of chips on a dedicated printed circuit board (PCB) substrate, with over 30 chips plus many passive components. So it is more accurately described as a System-in Package (SiP).<br />
This was confirmed when we took the S1 out of the case and x-rayed it;<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhTPEflS5MmTbHdkkgKVfIBfLISRxQ1Habcs70geCiHIwkXRxMCEhixnxF1K2xcjiCMS4Q1xN1Ozcmkjob-OsMLean2gs9qjoU-9dtg5bYI4Tzo1umNi7aURNbZSxjSh9nzFbojTjG52VCZ/s1600/02_0.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhTPEflS5MmTbHdkkgKVfIBfLISRxQ1Habcs70geCiHIwkXRxMCEhixnxF1K2xcjiCMS4Q1xN1Ozcmkjob-OsMLean2gs9qjoU-9dtg5bYI4Tzo1umNi7aURNbZSxjSh9nzFbojTjG52VCZ/s320/02_0.jpg" width="320" /></a></div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjXey2KjWdhefB8iMyjIfrhVwg-NSwNwX3w3CwVL-7o7YYht23DZ4uSsaL5Hb8GqNCaOMNPPD5MmGazbCVCoeSdjI6IxIQ3wnoKF9jFKGcKZJexUYOCKKe5AuDpUsKOf-1ttQq9lqx4_eVv/s1600/03_0.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjXey2KjWdhefB8iMyjIfrhVwg-NSwNwX3w3CwVL-7o7YYht23DZ4uSsaL5Hb8GqNCaOMNPPD5MmGazbCVCoeSdjI6IxIQ3wnoKF9jFKGcKZJexUYOCKKe5AuDpUsKOf-1ttQq9lqx4_eVv/s320/03_0.jpg" width="320" /></a></div>
<br />
And we identified many of them; <br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhjrXOQVzrXVCN6xcKn09coQua30WmQgLQybcriJJco6FPSdYb3W7naho7CoIvSDoxsdRTu1Y1xOokdJWbsbpACPweg7k7ahuUJ3H1iCkkRZcohVJNNUdRStuymb_IMwPjjXE-weFBQcj14/s1600/04_0.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="257" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhjrXOQVzrXVCN6xcKn09coQua30WmQgLQybcriJJco6FPSdYb3W7naho7CoIvSDoxsdRTu1Y1xOokdJWbsbpACPweg7k7ahuUJ3H1iCkkRZcohVJNNUdRStuymb_IMwPjjXE-weFBQcj14/s320/04_0.jpg" width="320" /></a></div>
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This gave us the teardown information that we needed to find what chips were used, but the S1 is so different from any of the other wearables that we have looked at, that we had to go in and see how it was put together. So cut it in two and then onto the polishing wheel, and we get an idea of what Apple’s assembly house has done for them.<br />
<br />
Actually, we did two cross-sections along the lines shown here;<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjFx6O8XhsyVCb4tzmRClMWYu-0hny3hLpL8UzmQPnl01tvk3UvEBHp-UkafzcvsFUs7rrVUPkAL_7ooLuSuos6wbTG62iqi7ZXH_qon87_G1u01rG84pUJ87mu6GlLN-TQ_RQ9Qtu63qxR/s1600/05_0.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="273" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjFx6O8XhsyVCb4tzmRClMWYu-0hny3hLpL8UzmQPnl01tvk3UvEBHp-UkafzcvsFUs7rrVUPkAL_7ooLuSuos6wbTG62iqi7ZXH_qon87_G1u01rG84pUJ87mu6GlLN-TQ_RQ9Qtu63qxR/s320/05_0.jpg" width="320" /></a></div>
<br />
This is section P1AS2;<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjofikmbGFORON9kt1OVv3UyGsWsKoeLpSUhIk9-Cb3U0wB-AbetVNBg1KnG6eRQWZQclbTEm4Xhxi4z1Sm9gMpZCK5i0x76WnuvvIaN2Ra9ZJFQhGE_9ZL9ENTV1sWQnTbaMgRImZZfTJu/s1600/07.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="22" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjofikmbGFORON9kt1OVv3UyGsWsKoeLpSUhIk9-Cb3U0wB-AbetVNBg1KnG6eRQWZQclbTEm4Xhxi4z1Sm9gMpZCK5i0x76WnuvvIaN2Ra9ZJFQhGE_9ZL9ENTV1sWQnTbaMgRImZZfTJu/s400/07.jpg" width="400" /></a></div>
<br />
On the left is the Dialog PMU; in the centre is the Apple APU (APL0778), with an Elpida DRAM co-packaged; and at the right is the Sandisk 64-Gb flash, including the controller chip and a spacer die. There seemed to be a wide-spread assumption that the APL0778 would be in a Package-on-Package (PoP) stack with the memory, as in the iPhones, but here it is in a straight-forward two-die stacked package.<br />
<br />
If we look closer, we can see that the S1 uses conventional assembly techniques, but once all the components are on the 4-layer PCB, the whole thing has been over-molded with more molding compound, and then plated with metal to give the stainless-steel looking finish. A close-up of the right edge shows what I mean;<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgJtIxl7YDRqQHDcREpXKhuJWK-E4tfNSnuqex7O2DWamVH0FkXAkYUvwg0Wf9m_G5d_I5Fq6nOs3Y1ZhNrBdBnF9FFgTJC-riXQ4ghKGalsMwvGqgUUzIukh0GcjAuY4xSVZ648__YPLPx/s1600/08.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="156" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgJtIxl7YDRqQHDcREpXKhuJWK-E4tfNSnuqex7O2DWamVH0FkXAkYUvwg0Wf9m_G5d_I5Fq6nOs3Y1ZhNrBdBnF9FFgTJC-riXQ4ghKGalsMwvGqgUUzIukh0GcjAuY4xSVZ648__YPLPx/s320/08.jpg" width="320" /></a></div>
<br />
There are two 32-Gb flash dies in a conventional package with its own substrate, which is flip-bonded onto the PCB, covered with the SiP over-molding, and the exterior is metallized, giving the silver finish. <br />
<br />
Section P1AS1 has the Broadcom BCM4334 in the centre, and the AMS NFC booster chip on the right. At left is a co-axial RF test socket.<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh6g4B9HjEzgKU8A1kDm86ZAisg_D5GOpLRDprEKJYhmu45SJ9qt425f1tMhRjPZfEAcziCEltTQ8_MibckOHA7bEGvbIx2L7Ob_py3RnYAkYZK79a4ylHZjEA6UXcXweX3i0t6hmtzUbFJ/s1600/10.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="26" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh6g4B9HjEzgKU8A1kDm86ZAisg_D5GOpLRDprEKJYhmu45SJ9qt425f1tMhRjPZfEAcziCEltTQ8_MibckOHA7bEGvbIx2L7Ob_py3RnYAkYZK79a4ylHZjEA6UXcXweX3i0t6hmtzUbFJ/s400/10.jpg" width="400" /></a></div>
<br />
Again, if we look closely, we can see that underfill has been used across the whole PCB before the over-molding was performed. Another feature of note is the I-shaped EMI shielding on the right of the BCM die, molded into the SiP – this is the first time we have seen this in any sort of package. In the x-ray image above, it surrounds the BCM chip, separating it from the other components. Here we are in close-up;<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhnAaTg6gN_pdimmlT0yKYTzfFkSXO5LLL9J8gs49k3qGLKMfeVR6NSox6pNHvnwhyjQ5rwGa7FOF-rA9FOX6T1ivhGwjPnSU0C6r6Mh-WTvCrFOEA7iP17fpu3m25vVDqC5owenvKCSTbV/s1600/11.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhnAaTg6gN_pdimmlT0yKYTzfFkSXO5LLL9J8gs49k3qGLKMfeVR6NSox6pNHvnwhyjQ5rwGa7FOF-rA9FOX6T1ivhGwjPnSU0C6r6Mh-WTvCrFOEA7iP17fpu3m25vVDqC5owenvKCSTbV/s320/11.jpg" width="297" /></a></div>
<br />
In effect the complete S1 assembly has EMI shielding since (with the exception of the accelerometer/gyro) the whole thing has a metal coat, mostly copper with a skin of iron/chromium. Such a coating will also inhibit moisture ingress, a good thing since I’ve heard tales of folks showering while wearing a Watch, and wrists can get a bit sweaty anyway.<br />
<br />
A big question for us is – who supplied such an innovative package? Press commentary has identified the provider as ASE (Advanced Semiconductor Engineering Inc.) of Taiwan; and I presented at an IMAPS wearables workshop back in June, and when I got to the Watch analysis the attendees from ASE shared a few knowing looks.<br />
<br />
The last quarterly analyst call from ASE also included this graphic, which details quite nicely the SiP concept, and includes details such as the EMI shielding:<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjotwaLz_MGAhCIj43uK2fVTM1OF7z-Fz1nzlTUZFK3bI9V9lqtFp-Gt2bbTJOtdMva4f5RRv4JfsXpaQfvZG9sFZfuqBIMsecYvNne5SRqBtYa1n2XrhY3uA7QdnSNkvsyKgFrQtxQnzBi/s1600/12.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="225" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjotwaLz_MGAhCIj43uK2fVTM1OF7z-Fz1nzlTUZFK3bI9V9lqtFp-Gt2bbTJOtdMva4f5RRv4JfsXpaQfvZG9sFZfuqBIMsecYvNne5SRqBtYa1n2XrhY3uA7QdnSNkvsyKgFrQtxQnzBi/s320/12.png" width="320" /></a></div>
<br />
ASE has also had more revenue from SiP this quarter, “In terms of overall, the SiP revenue accounted for about 22% in the second quarter, up from 15 a quarter ago because of the EMS SiP product ramp up.” Interestingly, they are also running below break-even on the SiP product (In response to a question as to whether all SiP projects are losing money, or just the one; “Thank God it is. It's only this particular project that is running below break-even. Other things are moving very nicely.”).<br />
<br />
Given these comments, I’m inclined to believe the press on this one – ASE is the supplier.<br />
<br />
Another nugget comes from perusing the transcript of the call – “What kind of application and what kind of customers you are working with for the new SiP projects?<br />
<br />
Tien Wu replied, “I don't think I'd comment specifically but I’m pretty sure you will find some new products that have come out pretty soon. Sorry.”<br />
<br />
He also noted, “We promise each other will never come out specific customers. So I will give you a non-qualifying, non-specific answer. We are expanding the SiP coverage to the cellphone, to the tablet in that particular arena. Hopefully, we can report more revenue, more penetration.”<br />
<br />
I take that to mean that we may well see this style of SiP in the new iPhone and iPad later this year – more fun!Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com3tag:blogger.com,1999:blog-5488132572864585098.post-88582265960861237852015-04-10T14:57:00.000-04:002015-04-10T14:58:51.991-04:00Apple Watch Launch Confirms WiFi and NFC Inside<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Arial","sans-serif";">Today (April 10) is
the day that the Apple Watch becomes available for order, and of course we will
be buying some to see what’s inside. We won’t be going for the gold Edition
model, even so some of us here would like to; the Sport version should be quite
good enough. </span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Arial","sans-serif";">At
the Apple event back on March 9 it was almost a case of last and least for the
Apple Watch, after listening through the ResearchKit and new MacBook launches, and
more Apple Pay demos. The Watch presentation was almost a case of <i style="mso-bidi-font-style: normal;">déjà vu</i>, since we got most of the
details last year in the announcement last September.</span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Arial","sans-serif";">The
one <i style="mso-bidi-font-style: normal;">new</i> technical detail that I did
pick up on was that the use of WiFi was confirmed – there was no mention of
that last year (time 74.00 in the </span><span style="font-family: "Arial","sans-serif";"><span style="color: blue;"><a href="http://www.apple.com/live/2015-mar-event/" target="_blank">March 9 video</a></span></span><span style="font-family: "Arial","sans-serif";">). There was
also much emphasis on the ability to use Apple Pay and make calls through the
Watch, so we know that there are microphones in there, and it has NFC
(near-field communications) capability, but we knew that after the initial
launch last year.</span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Arial","sans-serif";">The
WiFi news was interesting to us, since we did a </span><a href="http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/broadcom-wins-wifi-in-apple-watch/"><span style="font-family: "Arial","sans-serif";"><span style="color: blue;">pseudo-teardown</span></span></a><span style="font-family: "Arial","sans-serif";"> back then, based on Apple’s promo video,
and we came to the conclusion that the </span><a href="http://www.broadcom.com/products/Wireless-LAN/802.11-Wireless-LAN-Solutions/BCM4334"><span style="font-family: "Arial","sans-serif";"><span style="color: blue;">Broadcom BCM4334</span></span></a><span style="font-family: "Arial","sans-serif";"> was in the Watch. But no mention of
WiFi – what gives? I guess they just forgot, and even in the new launch it was
just a passing reference.</span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Arial","sans-serif";">We
identified the BCM4334 from a layout image of the board inside the Watch that
we took from a screen capture of the <a href="https://www.youtube.com/watch?v=y-waTi8BPdk" target="_blank">video</a>, and the characteristic footprint of
a flip-chip component.</span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjF7P-eYjvPLNUKgacccqN53mGAemVBEefRIlsLvZSJM5KKavXxRAnmwTuHwBNsa2ZWzCeh9sQGvVV-1tPeOn4bzaUondf2eA9SarniyJ4GOfN0s00z_2uq9J8YkzqxS3ZvsnN-LMbjADzc/s1600/S1+board-e.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjF7P-eYjvPLNUKgacccqN53mGAemVBEefRIlsLvZSJM5KKavXxRAnmwTuHwBNsa2ZWzCeh9sQGvVV-1tPeOn4bzaUondf2eA9SarniyJ4GOfN0s00z_2uq9J8YkzqxS3ZvsnN-LMbjADzc/s1600/S1+board-e.png" height="320" width="291" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Screen shot of PCB from Apple Watch - source: Apple film "<a href="https://www.youtube.com/watch?v=y-waTi8BPdk" target="_blank">Introducing Apple Watch</a>"</td></tr>
</tbody></table>
</div>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj-HZN0DFc-mKpYRqaCg_iLVsH1QdjPnBUUjFshjosyY_RMqTvKWlOmz5Ms2-okyRLV9GfTcrcf_VGVkhQOyc6dpLrMm_vwHPb3FwKfS6h1zfoXjC2MqOiWgqofCtEmD9S_7loCMZ3Obq5b/s1600/BCM4334.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj-HZN0DFc-mKpYRqaCg_iLVsH1QdjPnBUUjFshjosyY_RMqTvKWlOmz5Ms2-okyRLV9GfTcrcf_VGVkhQOyc6dpLrMm_vwHPb3FwKfS6h1zfoXjC2MqOiWgqofCtEmD9S_7loCMZ3Obq5b/s1600/BCM4334.png" height="207" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Broadcom BCM4334 die and position on Apple Watch PCB</td></tr>
</tbody></table>
<div class="MsoNormal" style="margin: 6pt 0in 0pt; text-align: center;">
</div>
<div class="MsoNormal" style="margin: 0in 0in 10pt;">
<span style="font-family: "Arial","sans-serif";">According to
Broadcom, “The BCM4334 is a single-chip dual-band combo device supporting
802.11n, bluetooth 4.0+HS & FM receiver. It provides a complete wireless
connectivity system with ultra-low power consumption for mass market smartphone
devices. Using advanced design techniques and 40nm process technology to reduce
active and idle power, the BCM4334 is designed to address the needs of highly
mobile devices that require minimal power consumption and compact size while
delivering dual-band Wi-Fi connectivity.”</span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Arial","sans-serif";">So
we have WiFi confirmed! In the meantime we’ve been looking at that board a
little more, and we have also confirmed that the NFC and NFC booster chips used
in the iPhone 6 and 6 Plus are also present.</span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Arial","sans-serif";">Again,
we looked at the footprints on the board – nothing quite as characteristic as
the Broadcom chip, but knowing the size of the chip package and the solder ball
array density gives us a good clue. And knowing the size of the BCM4334, we can work out the sizes of the other chips on the board.</span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Arial","sans-serif";">In
the iPhone 6 the NFC controller was a NXP 65V10, which contained the PN548 die,
and an AMS AS3923 NFC power booster; so it’s at least a possibility that Apple
will be using them in the Watch. </span><span style="font-family: "Arial","sans-serif";"> </span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Arial","sans-serif";">Below
is the AS3923 from the iPhone, showing the 5 x 4 solder ball grid on the bottom
of the part. Like the Broadcom chip, it is also a flip-chip-on-board (FCOB), so
the die size will be characteristic, and while a 5 x 4 grid is certainly not
unique, the combination of the two gives us reasonable confidence that a
matching footprint on the Watch board indicates the presence of an AS3923.<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhivrvm-kt33Q244rEpEQst6zzVU5LT9_tYPKAtFetLS9DY0VnlEf9HvgcsS0BYOAut4-lI-KVpgsvArvBHn-IHlT9kzI6OJjAseyVwkRqqanpx7jgiQxXcueBLfDRhHbtgKTyeHCaOacrv/s1600/Capture.PNG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhivrvm-kt33Q244rEpEQst6zzVU5LT9_tYPKAtFetLS9DY0VnlEf9HvgcsS0BYOAut4-lI-KVpgsvArvBHn-IHlT9kzI6OJjAseyVwkRqqanpx7jgiQxXcueBLfDRhHbtgKTyeHCaOacrv/s1600/Capture.PNG" height="148" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Top and bottom images of AMS AS3923</td></tr>
</tbody></table>
</span><br />
<div class="separator" style="clear: both; text-align: left;">
<span style="font-family: "Arial","sans-serif";"><span style="font-family: Times New Roman;">
</span><span style="font-family: "Arial","sans-serif";">Similarly
with the NXP 65V10:</span></span></div>
<span style="font-family: "Arial","sans-serif";">
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjkW4Y6sRnCLIqMaaDaXB1-r1tv9EnDo5aqZDHU47PZGhndZUi2UYmQF7Z4lK25fxdYGfakH-syjl7d8EfgvpFW_H2F8flcxfSlROk1gI7ciMaCFPMiX8rKtxZjM5eZLZXd9odwniZnoiWq/s1600/Capture2.PNG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjkW4Y6sRnCLIqMaaDaXB1-r1tv9EnDo5aqZDHU47PZGhndZUi2UYmQF7Z4lK25fxdYGfakH-syjl7d8EfgvpFW_H2F8flcxfSlROk1gI7ciMaCFPMiX8rKtxZjM5eZLZXd9odwniZnoiWq/s1600/Capture2.PNG" height="169" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Top and bottom images of NXP 65V10</td></tr>
</tbody></table>
</span><br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Arial","sans-serif";">Here
we have a 7 x 7 array, but it and the die size coincide with a footprint on the
PCB.</span></div>
</div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Arial","sans-serif";">Lastly,
a business contact pointed out that the motion sensing is likely done by the
same Invensense sensor that was used in the iPhones, the MP67B (probably the
MPU6700), and when we looked, again the size and solder pads match. We </span><a href="http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/comparing-the-invensense-and-bosch-accelerometers-found-in-the-iphone-6/"><span style="font-family: "Arial","sans-serif";"><span style="color: blue;">wrote about this</span></span></a><span style="font-family: "Arial","sans-serif";"> after the </span><a href="http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/inside-the-iphone-6-and-iphone-6-plus/"><span style="font-family: "Arial","sans-serif";"><span style="color: blue;">iPhone analysis</span></span></a>,<span style="font-family: Arial, Helvetica, sans-serif;"> and in its lowest power mode, it can draw less than 10 µA.</span><span style="font-family: "Arial","sans-serif";">
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiji1ZvtchygUJ6D5Xot-b8r91Oo9OqhBFYJSA4RXWKP2RsQF57aDIbI9925NoR0zO1mDWRw4u4P9ytN2La5Ff9fqUNopE0jvI2EI30ixNbmiCkUC3vJmjPCfN_DagpEML8-KJyTTFo0aHR/s1600/Capture3.PNG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiji1ZvtchygUJ6D5Xot-b8r91Oo9OqhBFYJSA4RXWKP2RsQF57aDIbI9925NoR0zO1mDWRw4u4P9ytN2La5Ff9fqUNopE0jvI2EI30ixNbmiCkUC3vJmjPCfN_DagpEML8-KJyTTFo0aHR/s1600/Capture3.PNG" height="156" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Top and bottom images of Invensense MP67B</td></tr>
</tbody></table>
</span></div>
<span style="font-family: "Arial","sans-serif";"></span><br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Arial","sans-serif";">Putting
these three together, we see below:</span><br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiRvbNcEVqwu3aUcJqK5Rodo2vuHyTSUvSSFj7qVHEH_oKXoxz7qPaQaMdBjm-6qLj8a5sW23P82OshXfiOJu9ori1rlNwRRr2WL-4WzHV3W5o6UuXLPGZN4NWHEVRL8dzUxLFNcnli-dtf/s1600/S1+board+Markup.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiRvbNcEVqwu3aUcJqK5Rodo2vuHyTSUvSSFj7qVHEH_oKXoxz7qPaQaMdBjm-6qLj8a5sW23P82OshXfiOJu9ori1rlNwRRr2WL-4WzHV3W5o6UuXLPGZN4NWHEVRL8dzUxLFNcnli-dtf/s1600/S1+board+Markup.png" height="292" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">PCB from Apple Watch showing Invensense, AMS, and NXP die positions</td></tr>
</tbody></table>
</div>
<span style="font-family: "Arial","sans-serif";">
</span><br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: "Arial","sans-serif";">Come
April 24 we will know what else is in there, as you can see that board is quite
packed. In the meantime, we’ll be looking for some more recognizable
components..<o:p></o:p></span></div>
Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.comtag:blogger.com,1999:blog-5488132572864585098.post-33602622881203981482015-04-06T11:34:00.000-04:002015-04-06T11:34:07.340-04:00Samsung’s FinFETs ARE in the Galaxy S6!The much anticipated Samsung Galaxy S6 made an early appearance in our teardown labs last week, thanks to the diligent skills of our trusted logistics guru. We got our hands on the 4G+ version, the SM-G920I, with what Samsung claims is the world’s first octa-core 64 bit operating system. There is a wide array of industry buzz surrounding this flagship smartphone, but from my process-oriented point of view the focal point has to be on the Exynos 7420 application processor.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi0bs5h3GYUERL7pZYdYPaeQj58WhNhIXUXM6kSBhg8yd9W2Bgq449RtAOAI8JbOr8zZo_01UREetEczhz09TiV_HFckYD7jivBW6leBvGZAvexKKMoEzbXdISNPzpwCEKbXv-QQch3oB2l/s1600/Teardown.bmp" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi0bs5h3GYUERL7pZYdYPaeQj58WhNhIXUXM6kSBhg8yd9W2Bgq449RtAOAI8JbOr8zZo_01UREetEczhz09TiV_HFckYD7jivBW6leBvGZAvexKKMoEzbXdISNPzpwCEKbXv-QQch3oB2l/s1600/Teardown.bmp" height="134" width="320" /></a><br />
</td></tr>
<tr><td class="tr-caption" style="text-align: center;">Samsung Galaxy S6 Teardown</td></tr>
</tbody></table>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiTOYe94cSzICuzBVFjiuxhTJ10xYuQQV0YJRMHwWXD4472iCKCopwfMggLYv6arBg3Ucsnfwr9_zhePk6jAlu-QW_rwC8KtEMsX5orbbb-M-erMMgQw1IkwsQ5tpjJN-PNgXJ3F90g06HD/s1600/New+Picture+(1).png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiTOYe94cSzICuzBVFjiuxhTJ10xYuQQV0YJRMHwWXD4472iCKCopwfMggLYv6arBg3Ucsnfwr9_zhePk6jAlu-QW_rwC8KtEMsX5orbbb-M-erMMgQw1IkwsQ5tpjJN-PNgXJ3F90g06HD/s1600/New+Picture+(1).png" height="320" width="149" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Galaxy S6 Motherboard</td></tr>
</tbody></table>
<h3>
Samsung Exynos 7420 Application Processor</h3>
The Samsung Exynos 7420 application processor is reportedly fabbed in Samsung’s 14 nm FinFET process. This is what Samsung has shown so far..<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjpjbqCL0w9Ui-NugAp0K_S7XOed2lqLfUUfTk6zhIOcFcTiV4kM1cNNVppkkKl_y2-GRQDRT2KTmKKD0XDv4TpHCc54-NoSg36UV7nig9qzgIGfIm7ZtDXo-juocAhLO3jkHr1nyqPNy2j/s1600/New+Picture.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjpjbqCL0w9Ui-NugAp0K_S7XOed2lqLfUUfTk6zhIOcFcTiV4kM1cNNVppkkKl_y2-GRQDRT2KTmKKD0XDv4TpHCc54-NoSg36UV7nig9qzgIGfIm7ZtDXo-juocAhLO3jkHr1nyqPNy2j/s1600/New+Picture.png" height="149" width="320" /></a></div>
<br />
Which is not exactly specific! To start with, here’s the package marking of the package-on-package:<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgjpoJ0Ul1Oxqlblf0FW5-n4zTKppypZJO4Q-MTTmhOTUB-KQuwt6dYWJmBY3qF4ICtLleOGWJcN3dnqh4p_D_0l_iexkJkr5t2ldi7JPyq0HNtTb5TJRmRCiPJu0oyJf3PtcV6sMP0HCT0/s1600/K3RG3G30MM-DGCH-c-a-br.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgjpoJ0Ul1Oxqlblf0FW5-n4zTKppypZJO4Q-MTTmhOTUB-KQuwt6dYWJmBY3qF4ICtLleOGWJcN3dnqh4p_D_0l_iexkJkr5t2ldi7JPyq0HNtTb5TJRmRCiPJu0oyJf3PtcV6sMP0HCT0/s1600/K3RG3G30MM-DGCH-c-a-br.png" height="283" width="320" /></a></div>
<br />
The layout of this is quite unusual – normally the memory marking (SEC 507 etc.) is in lines of text above the APU marking (7420 etc.), not in a diagonally opposed block. Which leads me into the speculation that maybe the 7420 is out of GLOBALFOUNDRIES, rather than a Samsung fab in Korea or Texas. Could ALB be short for Albany (NY)? Is the G in the lot code short for GLOBALFOUNDRIES? That all seems rather unlikely, but if Samsung wants to switch on the volume quickly in anticipation of huge volumes for the S6, what better way than to use three fabs? They did sound very confident in their last quarterly analyst call, saying that they expect 14-nm to be 30% of the LSI line capacity by year end. And there are lots of rumours about Qualcomm using the Samsung 14-nm process..<br />
<br />
The die photograph and the die mark confirm the use of the Exynos 7420:<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjsDvzhPAlayY0weOu_ekTEVR_CqYdGTp7ZfPiY1YHm4ReD6h4GEock-bi5pF4rhw6neah1iM0XbegAKhSEgiLdMZpy5Zr_jbRVqNwVT38MQOIHADRfLaWaPYf2QDzDJer8jT7E5qvwNPfN/s1600/7420_S5E7420A01_175707-s-br.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjsDvzhPAlayY0weOu_ekTEVR_CqYdGTp7ZfPiY1YHm4ReD6h4GEock-bi5pF4rhw6neah1iM0XbegAKhSEgiLdMZpy5Zr_jbRVqNwVT38MQOIHADRfLaWaPYf2QDzDJer8jT7E5qvwNPfN/s1600/7420_S5E7420A01_175707-s-br.png" height="320" width="315" /></a></div>
<div class="separator" style="clear: both; text-align: center;">
</div>
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjQFowBjHqggA0hN-jbsj7bSQGQW9556e7GNdTlq1dD-baEDpkHZ6HzaPTb-D2dBm0YAYjB05-oR-AAV4kX4Xjlm0gEI1ZDRhdDCkIA7GGWas5-WBV4BoTu4meUjXwQRCB-BKTvqlZbNzHe/s1600/Die+Mark.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjQFowBjHqggA0hN-jbsj7bSQGQW9556e7GNdTlq1dD-baEDpkHZ6HzaPTb-D2dBm0YAYjB05-oR-AAV4kX4Xjlm0gEI1ZDRhdDCkIA7GGWas5-WBV4BoTu4meUjXwQRCB-BKTvqlZbNzHe/s1600/Die+Mark.png" height="207" width="320" /></a></div>
<br />
The functional die size is ~78 mm2, which compares well with the ~118.3 mm^2 of the Snapdragon chip used in the Galaxy S5, and the 113 mm^2 size of the 20-nm Exynos 5433. If the 7420 was a straight shrink of the 5433, we’d expect it to be 55 – 60 mm^2, but the back-end metallization stack is reported to be similar to the 20-nm planar process, so a full 50% shrink is unlikely (and the analog regions never shrink as well as digital anyway). We’ll have to wait until we see the floorplan to see how much functionality the two parts have in common.<br />
<br />
Our guys in the lab made their usual exceptional effort in enabling us to see what the process looks like – within a few hours of getting the phone in-house, we have a decapsulated part and a cross-sectional sample under the microscope.<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiQs3aZY-lyadj0wnNC6emkaGqmB_lIXMWonWi5cZVftHL7bLL2pFmT_Gxrjat394LT1Lvt8LfukFtPp_dc-gIgAdSfe3iv8Yl9Mw3Fw2xU4DocASmbEiMulGir1rsbQ-UILPTx4pMSfO2E/s1600/New+Picture+(1).png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiQs3aZY-lyadj0wnNC6emkaGqmB_lIXMWonWi5cZVftHL7bLL2pFmT_Gxrjat394LT1Lvt8LfukFtPp_dc-gIgAdSfe3iv8Yl9Mw3Fw2xU4DocASmbEiMulGir1rsbQ-UILPTx4pMSfO2E/s1600/New+Picture+(1).png" height="227" width="320" /></a></div>
<br />
The Exynos 7420 uses 11 layers of metal, as you can see from the die seal cross-section above. Now let’s look at the transistors:<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgZhzkRhALm0IRhQMmo5vHBZ4sPK3UuaZM_LfGelFO5wgnTxHRdcS0rJbEAGTfZ4JG2qAnEIMyNEoJkD2xahwmWTb0M5uPcikGwf3BgSCIK0nFa5wQNEc8Cziwu1oqQpRpcsFr9vj1lmSaf/s1600/New+Picture+(3).png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgZhzkRhALm0IRhQMmo5vHBZ4sPK3UuaZM_LfGelFO5wgnTxHRdcS0rJbEAGTfZ4JG2qAnEIMyNEoJkD2xahwmWTb0M5uPcikGwf3BgSCIK0nFa5wQNEc8Cziwu1oqQpRpcsFr9vj1lmSaf/s1600/New+Picture+(3).png" height="214" width="320" /></a></div>
<br />
And we do have finFETs! This section is parallel to the fins, and across the gates. The bottoms of the contacts approximately indicate the top edge of the fin, and we are seeing the gates wrapped over and further down the sidewalls of the fin than the contacts appear to go. We will need another section orthogonal to this one to see if we have the type of epi growth in the source-drains that Intel uses.<br />
<br />
This makes Samsung the second in line to get finFETs into volume production; they have successfully taken their 20-nm, first-generation, gate-last, high-k, metal-gate stack and adapted it to a first generation fin structure. We will need more detailed images to see whether the fins have vertical or sloped sidewalls, and how close to the Intel model they are, but those will come in the fullness of time when we have completed our full analysis and published our report.<br />
<br />
Meanwhile, keep an eye on the blog!Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-30132646682245231832014-12-18T01:23:00.002-05:002014-12-18T01:23:44.306-05:00IEDM – Monday was FinFET DayIn my conference <a href="http://electroiq.com/chipworks_real_chips_blog/2014/12/08/iedm-2014-preview/" target="_blank">preview blog</a> last week I mentioned that session 3 on the Monday afternoon would be a hot session, with three finFET papers, by TSMC, Intel, and IBM. I was right – even though they were given in the Grand Ballroom, it was full.<br />
<br />
Paper 3.1 from TSMC disclosed what looks like their 16FF+ 16-nm finFET technology, advanced from the 16FF reported last year – although they don’t actually call it that in the paper. A 15% speed boost and 30% power reduction is claimed, or <a href="http://www.tsmc.com/english/dedicatedFoundry/technology/16nm.htm" target="_blank">40% speed gain and 60% power saving compared to the 20-nm process</a>.<br />
<br />
Gossip in the industry has it that 16FF was not advanced enough for TSMC’s customers, so they did some transistor engineering and cranked up the performance; 16FF is not even mentioned on the website these days, and <a href="http://www.tsmc.com/uploadfile/ir/BusinessRelease/1112%20TSMC%2016FFplus%20E.pdf" target="_blank">16FF+ is now in risk production, with endorsements by Avago, Freescale, LG Electronics, MediaTek, Nvidia, Renesas and Xilinx.</a><br />
<br />
The 48 nm fin pitch and 90 nm contacted gate pitch announced last year were maintained, as is the 1x metal pitch of 64 nm. This level uses “advanced patterning scheme” – presumably self-aligned double patterning (SADP), whereas the other 80/90 nm pitch metals are done with single patterning. <br />
<br />
The low-k dielectric stack has been optimized relative to the 16FF process to give almost 10% capacitance improvement, and they have also added a planar high-k MIM capacitor (>15 fF/um2) for on-chip noise reduction.<br />
<br />
At the transistor level, we have a dual-gate oxide process, replacement metal gate (gate-last), dual epitaxial raised source/drains, and tungsten local interconnect – but NO PICTURES! Lots of plots, but no transistor images, as in last year’s 16FF paper, and we were out of luck in the live presentation as well.<br />
<br />
So we still have no idea of what the TSMC finFETs will look like. I guess that’s good for me and Chipworks, since we’ll have to wait until they actually show up in the real world sometime next year.<br />
<br />
Intel gave a late news paper (3.7) describing their 14-nm finFET (note – finFET, not trigate) process at 4.05 pm. Being late news, there were only 15 minutes for Sanjay Natarajan to describe what looks like a technology that is distinctly changed from the 22-nm process. AND there were images!<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgtccG8asaZU30uXyc7ndJaGsVVk4EsTWh95vPfecTYUoP6WquHPQv0WsMNS2BDDnpdPNY0COyd9CPRFOhAZku9N4J28su7hwSMEsV9MbrdDSU3MlOCJ-Su-kriDqGfV92VWb89fiBrmf5J/s1600/3.7-1.PNG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgtccG8asaZU30uXyc7ndJaGsVVk4EsTWh95vPfecTYUoP6WquHPQv0WsMNS2BDDnpdPNY0COyd9CPRFOhAZku9N4J28su7hwSMEsV9MbrdDSU3MlOCJ-Su-kriDqGfV92VWb89fiBrmf5J/s1600/3.7-1.PNG" height="208" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Intel images of 14-nm NMOS fins and gates</td></tr>
</tbody></table>
<br />
As announced <a href="http://files.shareholder.com/downloads/INTC/3570266827x0x775635/ae87f50f-2f66-4ab7-b35f-bd98ab44b43f/Intel_14nm_Aug11.pdf" target="_blank">back in August</a>, fin pitch is reduced to 42 nm, contacted gate pitch to 70 nm, and 1x metal to 52 nm, and we confirmed these on the Broadwell chip that we pulled out of a Panasonic laptop. In addition to the fins, the gates and the minimum metal levels use SADP, making for complex front-end lithography.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjoo7tAtthc8o35mv-m0oglaC8Wg6a5lnPg7MZIUvyzxdF_21cbYAyADbgrhcfD4QTQlXV6e2tcID5jNCcjJPp2xTi2akuqMmzl4T-7WTacv1HtDGnuLrJ7sna8ZAbZgVC1QctKkwsedM5b/s1600/3.7-2.bmp" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjoo7tAtthc8o35mv-m0oglaC8Wg6a5lnPg7MZIUvyzxdF_21cbYAyADbgrhcfD4QTQlXV6e2tcID5jNCcjJPp2xTi2akuqMmzl4T-7WTacv1HtDGnuLrJ7sna8ZAbZgVC1QctKkwsedM5b/s1600/3.7-2.bmp" height="326" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Intel 14-nm pitches</td></tr>
</tbody></table>
The fins have been modified from the 22-nm process to have a more vertical profile, slimmed down to 8 nm wide, and Intel also claims a “novel sub-fin doping technique” using “solid-source doping to enable better optimization of punch-through stopper dopants”. Sanjay’s presentation revealed that the solid-source doping uses a doped glass; now it’s down to us to work out when and where it’s used for punch-through inhibition. Idsat is claimed to improve by 15% for NMOS and 41% for PMOS over 22nm, and Idlin by 30% for NMOS and 38% for PMOS.<br />
<br />
Changes have also been made to the back end – low-k dielectrics are used in the first eight levels, and significantly we see the first use of air-gaps in the M4 and M6 levels (80 and 160-nm pitch). This is Intel’s SEM image from the paper:<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgLpzn4B1Pbs_JUX6RDdkfn_Qr1SKFtk_U9K8zC95YHgWy6o3oRRCQLx3D_qa0dBjKPTcEB0sGe4XIDbEgK1Wz8OWGmGOWXMDKfv6Pa2Uq8sV692Q7GhhoAD08Vopt19erSfbwvjvf-1AhL/s1600/3.7-3.bmp" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgLpzn4B1Pbs_JUX6RDdkfn_Qr1SKFtk_U9K8zC95YHgWy6o3oRRCQLx3D_qa0dBjKPTcEB0sGe4XIDbEgK1Wz8OWGmGOWXMDKfv6Pa2Uq8sV692Q7GhhoAD08Vopt19erSfbwvjvf-1AhL/s1600/3.7-3.bmp" height="300" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">SEM image of Intel air-gaps</td></tr>
</tbody></table>
And here’s a TEM image from our analysis:<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgoEuRYfUJ1Fg5QAFrD2LyNdvzOH8YodxzDfkap5cVUVkeyLte0WO27Q-1YJpYmTChlLkV3FD1JHJKlF_VciN-L9cSMGcjP7ltC945HwBz-YoOgZIbyOajRUKhLiDPa9JvVFk7iYD6n3EAP/s1600/Intel+airgaps2.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgoEuRYfUJ1Fg5QAFrD2LyNdvzOH8YodxzDfkap5cVUVkeyLte0WO27Q-1YJpYmTChlLkV3FD1JHJKlF_VciN-L9cSMGcjP7ltC945HwBz-YoOgZIbyOajRUKhLiDPa9JvVFk7iYD6n3EAP/s1600/Intel+airgaps2.png" height="333" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">TEM image of Intel air-gaps</td></tr>
</tbody></table>
We can see from the spacing of the gaps and the profile of the barrier layer over the copper that a patterned approach has been taken, as described in the IITC 2010 paper [1], using a mask step after the formation of the metal seal layer. <br />
<br />
Intel likes to point out their history – this is the second generation finFET, fourth generation HKMG, and sixth generation strained silicon; will their 10-nm be the third, fifth, and seventh generations? <br />
<br />
I’m now inclined to think so, since at an Applied Materials event in the evening, when asked about the delay in the 14 nm launch, Mark Bohr was heard to say “We won’t have similar problems at 10 nm”. Mark does not make such comments lightly, so to me that implies two things – the 10-nm process is pretty well locked down already, and it’s unlikely that there are huge structural changes from the 14-nm generation. Indeed, the aggressive shrink from 22 nm to 14 nm puts them well on the way to the predicted 10-nm feature sizes.<br />
<br />
Immediately after Intel’s talk IBM had their 15 minutes of IEDM advanced CMOS fame, describing their 14-nm technology. This has their fourth generation embedded DRAM, but is the first-gen finFET, and the first-gen gate-last process (and I’ve lost count of the SOI generations). <br />
<br />
IBM claims a “unique dual workfunction process applied to both NFETs and PFETs” and sub-20-nm gate lengths, which will be the smallest we’ve seen if we ever get a sample. Being IBM, the intended product will be over 600 mm2 and have 15 metal levels, presumably their Power9 server chip.<br />
<br />
Fin pitch is the same as Intel at 42 nm, but contacted gate pitch is 80 nm, and 1x metal is 64 nm. Here the fins are completely isolated since they are on the buried oxide, so no punch-through implants are needed at the base of the fin as on a bulk silicon substrate.<br />
<br />
We do have pictures – these are really fuzzy, but we can see the gate wrapped over the fin with slightly raised source/drains on either side, and some nice facets on the source/drain epi.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhlabAyZQ251p2o2ENnoW-EDcL1mdaMQXGF9lDt9WRv0mfLaeUK_SdUydFmf2Vw3ukCuqFe2Wjzb-cfMXY2oGl42HuWvQ7hkayNr63aBwWtuFWiNE2jlUf7dFThROx6oJeTj-THkfO5qpVz/s1600/IBM3-8-1.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhlabAyZQ251p2o2ENnoW-EDcL1mdaMQXGF9lDt9WRv0mfLaeUK_SdUydFmf2Vw3ukCuqFe2Wjzb-cfMXY2oGl42HuWvQ7hkayNr63aBwWtuFWiNE2jlUf7dFThROx6oJeTj-THkfO5qpVz/s1600/IBM3-8-1.png" height="221" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">IBM gate and P-type source/drain epi</td></tr>
</tbody></table>
During the presentation there were (of course) no details of the work-function materials, but it was stated that two masks were used to make the dual work-function structure; so presumably two slightly different material sets for the different work-functions. Another tidbit was that the pass-gate transistors in the e-DRAM had a different Vt than the logic transistors, but not achieved by a workfunction change.<br />
<br />
I’d missed it, but the IBM alliance gave a paper at the VLSI conference back in June [2], where they describe a 10-nm finFET process; this look likes the same process, backed off to 14 nm and with the e-DRAM added.<br />
<br />
The e-DRAM introduces some challenges in connecting the trench capacitor plate to the fin of the pass gate. In the planar 22-nm version there is a polySi strap from the polySi in the trench to the SOI on the buried oxide; in the finFET design the polySi strap is still used, but it is formed as a plug on the trench fill connecting to the SOI layer before fin definition, and the plug is etched into a fin during the fin etch. The epi module has been tuned to minimise the strap resistance and therefore the effect on access time. <br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjnbAANiwoc9eB_bJ62s3clqBekOaA_Rr2pRtQJUsVzcOBZva2YpkQIkJmitV36A9Xo1_duGsNrXFQdD3FdLTOfQu50y-98eTMhBdub-52WsJW-2MYdHUKLK7Z5j-TLDcqvUpFaHZi60WqM/s1600/IBM3-8-2.bmp" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjnbAANiwoc9eB_bJ62s3clqBekOaA_Rr2pRtQJUsVzcOBZva2YpkQIkJmitV36A9Xo1_duGsNrXFQdD3FdLTOfQu50y-98eTMhBdub-52WsJW-2MYdHUKLK7Z5j-TLDcqvUpFaHZi60WqM/s1600/IBM3-8-2.bmp" height="400" width="331" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Schematic of IBM e-DRAM trench capacitor strap to finFET</td></tr>
</tbody></table>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhnUWZ5qFRZiUlA3Tghs05q68lhzDlPZV94ujTigTGaPcyqT1Xpm_MgqTfatsRITeubZ5liZekH3Ff4mjqUuYNO7jo7qEGH2ClaJ3rO5ak1louYdcz_NdzN8XDJMuRZpk1im7fsHsFJuUns/s1600/IBM3-8-3.bmp" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhnUWZ5qFRZiUlA3Tghs05q68lhzDlPZV94ujTigTGaPcyqT1Xpm_MgqTfatsRITeubZ5liZekH3Ff4mjqUuYNO7jo7qEGH2ClaJ3rO5ak1louYdcz_NdzN8XDJMuRZpk1im7fsHsFJuUns/s1600/IBM3-8-3.bmp" height="338" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Plan-view TEM image of IBM trench capacitor strap</td></tr>
</tbody></table>
<br />
Cell size of the eDRAM is now 0.0174 um2; and if the trench capacitors are coupled together without the select gates, they can provide on-chip decoupling capacitors with a value of 450 fF/um2.<br />
<br />
In the back-end IBM has their fifteen layers of metal ranging from 1x – 40x, and the section shows that the 40x is seriously thick, to take the power needed to run a chip this size!<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjQyjS56pVz9Wi4u4jKl4vZcOrjASdPB5OV2YGxz_gXUz3_4F-6XjeU14kSwj3uEEp0cYI0P3LEHhLmzP8mo3YbSx40kcOJeOeuivTpZQmg2-XRHtGafntGIaru6R3pu5mBRtWpKloE1uQD/s1600/IBM3-8-4.bmp" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjQyjS56pVz9Wi4u4jKl4vZcOrjASdPB5OV2YGxz_gXUz3_4F-6XjeU14kSwj3uEEp0cYI0P3LEHhLmzP8mo3YbSx40kcOJeOeuivTpZQmg2-XRHtGafntGIaru6R3pu5mBRtWpKloE1uQD/s1600/IBM3-8-4.bmp" height="400" width="311" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Metal stack in IBM 14-nm fin FET process</td></tr>
</tbody></table>
All that made for an eventful afternoon, with a bit of a disappointment from TSMC; we’ll look forward to seeing both their finFET and the Power9 next year. Of course we have a <a href="https://chipworks.secure.force.com/catalog/ProductDetails?sku=INT-SR217&viewState=DetailView&cartID=&g=&parentCategory=&navigationStr=CatalogSearchInc&searchText=Broadwell" target="_blank">suite of reports </a>on the Intel Broadwell, for those who want a detailed analysis of the part!<br />
<br />
<strong>References</strong><br />
[1] H.J. Yoo et al., “Demonstration of a reliable high-performance and yielding Air gap interconnect process”, IITC 2010, pp. 1-3 <br />
[2] K-I Seo et al., “A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI”, VLSI Tech 14, pp. 12-13Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-9629214102859641412014-12-05T12:38:00.000-05:002014-12-08T16:02:58.934-05:00IEDM 2014 Preview - What's Coming Up On 13 - 17 December<span lang="EN-GB">Later this month the
good and the great of the electron device world will make their usual
pilgrimage to San Francisco for the </span><span lang="EN-US" style="mso-ansi-language: EN-US;">2014 </span><span lang="EN-GB"><a href="http://www.his.com/~iedm"><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">IEEE International Electron Devices
Meeting</span></span></a></span><span lang="EN-US" style="mso-ansi-language: EN-US;">.<span style="mso-spacerun: yes;"> </span>To quote the conference web front page, IEDM
is “</span><span lang="EN-GB">the world’s pre-eminent forum for reporting
technological breakthroughs in the areas of semiconductor and electronic device
technology, design, manufacturing, physics, and modeling. IEDM is the flagship
conference for nanometer-scale CMOS transistor technology, advanced memory,
displays, sensors, MEMS devices, novel quantum and nano-scale devices and
phenomenology, optoelectronics, devices for power and energy harvesting,
high-speed devices, as well as process technology and device modeling and
simulation. The conference scope not only encompasses devices in silicon,
compound and organic semiconductors, but also in emerging material systems.
IEDM is truly an international conference, with strong representation from
speakers from around the globe.”<span style="mso-spacerun: yes;"> </span><o:p></o:p></span><br />
<br />
<span lang="EN-GB">That’s a pretty
broad range of topics, but from my perspective at <a href="http://www.chipworks.com/"><span style="color: blue;">Chipworks</span></a>, focused on the analysis of chips
that have made it to production, it’s the conference where companies strut
their technology, and post some of the research that may make it into real
product in the next few years.<o:p></o:p></span><br />
<br />
<span lang="EN-GB">In the last few
days I’ve gone through the <a href="http://www.his.com/~iedm/program/14advprg.pdf"><span style="color: blue;">advance program</span></a>, and
here’s my look at what’s coming up, in more or less chronological order.<span style="mso-spacerun: yes;"> </span>As usual there are overlapping sessions with
interesting papers in parallel slots, but we’ll take the decision as to which
to attend on the conference floor.<o:p></o:p></span><br />
<br />
<br />
<b style="mso-bidi-font-weight: normal;"><span lang="EN-GB">Saturday/Sunday<o:p></o:p></span></b><br />
<br />
<span lang="EN-GB">Again this year
the conference starts on the Saturday afternoon, with a set of six 90-minute
tutorials on a range of leading-edge topics:<o:p></o:p></span><br />
<br />
<ul>
<li><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/tut-1-vandervorst.pdf"><i style="mso-bidi-font-style: normal;"><span style="color: blue;">Physical characterization of novel
materials and devices for logic and memory</span></i></a>, W.Vandervorst, imec</span><span lang="EN-US" style="mso-ansi-language: EN-US;"><o:p></o:p></span></li>
<li class="MsoNormal" style="margin: 6pt 0in 0pt; mso-list: l1 level1 lfo1;"><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/tut-1-omura.pdf"><i style="mso-bidi-font-style: normal;"><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Power Semiconductor Device Basics: History, Application, and
Physics</span></span></i></a></span><i style="mso-bidi-font-style: normal;"><span lang="EN-US" style="mso-ansi-language: EN-US;">,</span></i><span lang="EN-US" style="mso-ansi-language: EN-US;"> Ichiro Omura, Kyushu Institute of
Technology <o:p></o:p></span></li>
<li class="MsoNormal" style="margin: 6pt 0in 0pt; mso-list: l1 level1 lfo1;"><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/tut-1-avouris.pdf"><i style="mso-bidi-font-style: normal;"><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Optoelectronics of Graphene and other 2D materials</span></span></i></a></span><i style="mso-bidi-font-style: normal;"><span lang="EN-US" style="mso-ansi-language: EN-US;">, </span></i><span lang="EN-US" style="mso-ansi-language: EN-US;">Phaedon
Avouris, IBM Research, T.J. Watson Research Center <o:p></o:p></span></li>
<li class="MsoNormal" style="margin: 6pt 0in 0pt; mso-list: l1 level1 lfo1;"><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/tut-2-cartier.pdf"><i style="mso-bidi-font-style: normal;"><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Reliability characteristics of CMOS transistors post
Si/SiO2/poly-Si gate stack scaling</span></span></i></a></span><i style="mso-bidi-font-style: normal;"><span lang="EN-US" style="mso-ansi-language: EN-US;">,</span></i><span lang="EN-US" style="mso-ansi-language: EN-US;">
Eduard Cartier, IBM Research, T.J. Watson Research Center <o:p></o:p></span></li>
<li class="MsoNormal" style="margin: 6pt 0in 0pt; mso-list: l1 level1 lfo1;"><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/tut-2-driesen.pdf"><i style="mso-bidi-font-style: normal;"><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Power Electronics for a Smart Energy Future</span></span></i></a></span><i style="mso-bidi-font-style: normal;"><span lang="EN-US" style="mso-ansi-language: EN-US;">,</span></i><span lang="EN-US" style="mso-ansi-language: EN-US;"> Johan
Driesen, KU Leuven, ESAT-ELECTA <o:p></o:p></span></li>
<li class="MsoNormal" style="margin: 6pt 0in 0pt; mso-list: l1 level1 lfo1;"><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/tut-2-vanhoudt.pdf"><i style="mso-bidi-font-style: normal;"><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Nonvolatile Memories: old and new</span></span></i></a></span><i style="mso-bidi-font-style: normal;"><span lang="EN-US" style="mso-ansi-language: EN-US;">,</span></i><span lang="EN-US" style="mso-ansi-language: EN-US;"> Jan
Van Houdt, imec <o:p></o:p></span></li>
</ul>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">The first three
are from 2.45 – 4.15, and the remainder from 4.30 – 6.00.<span style="mso-spacerun: yes;"> </span>This year I hope to make it to my old friend
Wilfried Vandervorst’s session on characterisation, and possibly the other imec
tutorial on memories at 4.30. <o:p></o:p></span></div>
<br />
<span lang="EN-GB">Wilfried gave an
impressive talk at the imec symposium at Semicon West, and this time he has an
hour and a half instead of 45 minutes, so hopefully a good bit more detail on
what we can see, now that we are counting atoms in transistor analysis.<o:p></o:p></span><br />
<br />
<span lang="EN-GB">On Sunday
December 14<sup>th</sup>, we start with the <a href="http://www.his.com/~iedm/program/courses.html"><span style="color: blue;">short courses</span></a>, <a href="http://www.his.com/~iedm/program/14_sc_glance.htm"><span style="color: blue;">“<b style="mso-bidi-font-weight: normal;">Challenges of 7nm CMOS Technologies</b>” and “<b><span lang="EN-US" style="mso-ansi-language: EN-US;">3D System Integration Technology</span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">”</span></span></a>.
Last year the short course was “Challenges of 10nm and 7nm CMOS Technologies”,
so I guess we’ve moved on a bit; though I still need convincing that the 10-nm
process architectures are locked down as yet.<o:p></o:p></span><br />
<br />
<span lang="EN-GB">Hidenobu Fukutome of Samsung</span><span lang="EN-GB" style="mso-ansi-language: EN-US;"> </span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">has organised the
former, and we have some impressive speakers – </span><span lang="EN-US" style="mso-ansi-language: EN-US;">Greg Yeric, Senior Principal Design Engineer of
ARM</span><span lang="EN-GB" style="mso-bidi-font-weight: bold;">, (</span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/Yeric.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Circuit application requirements</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">), Peide
Ye, Purdue University (</span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/Ye.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Device challenges</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">), </span><span lang="EN-US" style="mso-ansi-language: EN-US;">Guido Groeseneken, KU Leuven &
imec<span style="mso-bidi-font-weight: bold;">, (</span></span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/Groeseneken.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Reliability challenges</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">), </span><span lang="EN-US" style="mso-ansi-language: EN-US;">Eric Karl, Intel</span><span lang="EN-GB">, (<a href="http://www.his.com/~iedm/program/karl.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">On-die memory challenges</span></span></b></a><span style="mso-bidi-font-weight: bold;">)</span></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">, and </span><span lang="EN-US" style="mso-ansi-language: EN-US;">Tsutomu Tezuka, Advanced LSI
Technology Laboratory, Toshiba<span style="mso-bidi-font-weight: bold;"> (</span></span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/Tezuka.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Process and integration challenges</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">). With
14-nm product on the market now, we need to look ahead, so this is appropriate
- on the Intel clock, 7-nm is only four – five years away!<span style="mso-spacerun: yes;"> </span><o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">It now seems that 10-nm will be silicon-based, so
we’ll see what the guys predict for 7-nm; new channel materials, nanowire
transistors, and how will they integrate into a manufacturable process? What
will be the effects on the performance of the basic logic blocks? What will
device reliability be like with the potential new materials/structures? Hopefully
we’ll find out here!<b><o:p></o:p></b></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Eric Beyne of imec has set up the other short
course; 3D is a very hot topic these days, both finFET and die stacking – here
we are talking about die stacking.<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Denis Dutoit of Cea-Leti<b> </b>looks at </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/dutoit.pdf"><span style="color: blue;"><b><span lang="EN-US" style="mso-ansi-language: EN-US;">3D System Design - Challenges for 3D
Integration</span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">;</span></span></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> I have the distinct
impression that the manufacturing technology is in place, but design and test
still have a way to go. <o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Next up is Kangwook Lee, Tohoku U, on </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/Lee.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Enabling Technologies: TSV
Technology</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">; again TSV technology is being promoted as here by
both foundries and OSATs, and some products such as the Xilinx 2.5D FPGAs are
out there, and stacked memories such as the Hybrid Memory Cube are sampling.<b><o:p></o:p></b></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">After lunch we have 3D evangelist
extraordinaire Subu Iyer from IBM, talking about </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/Iyer.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Enabling technologies: 3D integration for the
Memory subsystem</span></span></b></a></span><b><span lang="EN-US" style="mso-ansi-language: EN-US;">. </span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">IBM has been embedding DRAM into their products for several generations
now, and as noted above, we are starting to see 3D-packaged memory come on to
the market.<o:p></o:p></span><br />
<br />
<span lang="EN-GB"><a href="http://www.his.com/~iedm/program/Lu.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Wafer-to-wafer bonding</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is an
essential part of 3D stacking, and that’s the topic of James Lu from Rensselaer
Polytechnic. The last session is on </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/Croes.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">3D Reliability and Impact of 3D Integration on
Devices</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">, with Kristof Croes of imec discussing the device
effects of the additional processing needed to make a 3D stack.<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">So some good solid stuff – although the
courses make a long Sunday, from 9 a.m. to 5.30 p.m., but it’s worth sticking
around to the end.<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Sunday evening has some extra sessions;
Sematech is holding a session on “<b>Materials & Technologies for Beyond
CMOS</b>” at an as-yet unnamed location; and Leti will host a workshop on their
“</span><span lang="EN-GB"><a href="http://leti2014-iedm.insight-outside.fr/"><b><span style="color: blue;">vision
for silicon nano-technologies in the next 10 years</span></b></a><span style="mso-bidi-font-weight: bold;">” from 5.30 – 8.30 pm at the Nikko Hotel,
across the street from the Hilton.<o:p></o:p></span></span><br />
<br />
<br />
<b><span lang="EN-GB">Monday</span></b><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><o:p></o:p></span></b><br />
<br />
<span lang="EN-GB">Monday morning we have the <b style="mso-bidi-font-weight: normal;">plenary
session</b>, with three pertinent talks on the challenges of contemporary
electronics: <o:p></o:p></span><br />
<ul>
<li>
<b><i style="mso-bidi-font-style: normal;"><span lang="EN-US" style="mso-ansi-language: EN-US;">SiC MOSFET Development for Industrial Markets</span></i></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">, John Palmour, Cree Inc. – broadening the range of uses for silicon carbide? </span><span lang="EN-US" style="mso-ansi-language: EN-US;"><o:p></o:p></span></li>
<li><b><i style="mso-bidi-font-style: normal;"><span lang="EN-US" style="mso-ansi-language: EN-US;">Are 3D atomic printers around the corner? </span></i></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Enrico Prati, CNR IMM (Italy’s Institute for Microelectronics and Microsystems) – now that 3D printers are becoming consumer goods, can we push the idea into the atomic scale? That sounds like the potential for everything from drugs design to the ultimate version of Moore’s law..</span><span lang="EN-US" style="mso-ansi-language: EN-US;"><o:p></o:p></span></li>
<li class="MsoNormal" style="margin: 0in 0in 0pt; mso-list: l2 level1 lfo2; tab-stops: list .5in;"><b><i style="mso-bidi-font-style: normal;"><span lang="EN-US" style="mso-ansi-language: EN-US;">Research into ADAS with Driving Intelligence for Future Innovation</span></i></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">, Hideo Inoue, Toyota – Automated Driver Assistance Systems; moving towards the self-driving car?</span><span lang="EN-US" style="mso-ansi-language: EN-US;"><o:p></o:p></span></li>
</ul>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">After lunch we
have seven parallel sessions coming up! <o:p></o:p></span></div>
<br />
<span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s2.pdf"><b style="mso-bidi-font-weight: normal;"><span style="color: blue;">Session 2</span></b></a> is a focus session on power devices, with a kick-off
paper by John Baliga of NCSU, on the <b style="mso-bidi-font-weight: normal;">Social
Impact of Power Semiconductor Devices (2.1)</b>. John invented the IGBT in his
time at GE back in the 80’s, and claims that the technology has reduced global
carbon dioxide emissions by 75 trillion pounds over the last 30 years. He
speculates that this can only increase with the introduction of new power devices.
Papers <b style="mso-bidi-font-weight: normal;">2.3</b> – <b style="mso-bidi-font-weight: normal;">2.5</b> and <b style="mso-bidi-font-weight: normal;">2.7</b> look like
reviews of high-power switch technologies, and Si-, SiC and GaN-based power
devices, respectively, while <b style="mso-bidi-font-weight: normal;">2.2</b> and
<b style="mso-bidi-font-weight: normal;">2.6</b> look at specific SiC JFET and
GaN HEMT devices.<o:p></o:p></span><br />
<br />
<b style="mso-bidi-font-weight: normal;"><span lang="EN-GB">Session 3</span></b><span lang="EN-GB"> is the hot <a href="http://www.his.com/~iedm/program/session/s3.pdf"><b style="mso-bidi-font-weight: normal;"><span style="color: blue;">Advanced CMOS Technology</span></b></a> group of papers with late news
additions by Intel <b style="mso-bidi-font-weight: normal;">(3.7)</b> and IBM <b style="mso-bidi-font-weight: normal;">(3.8)</b>, both on 14-nm finFET
technologies, which even triggered their own <a href="http://www.btbmarketing.com/iedm/releases/late-news%20release%20IEDM%202014_final.pdf"><span style="color: blue;">press
release</span></a>. <o:p></o:p></span><br />
<br />
<span lang="EN-GB">The Intel finFET
(note – not trigate!) device features “a novel subfin doping technique” to
minimise fin doping and leakage under the fins, and air-gaps in two
metallisation levels. This is the first use of air-gaps in a production logic
part that I know of; we’ve seen them in memory chips for a while. Intel had a
persuasive paper on this at the 2010 IITC conference [1], and I was wondering
if we would see implementation at this node.<o:p></o:p></span><br />
<br />
<span lang="EN-GB">If you hunt hard
in <a href="http://files.shareholder.com/downloads/INTC/3648454336x0x775635/AE87F50F-2F66-4AB7-B35F-BD98AB44B43F/Intel_14nm_Aug11.pdf"><span style="color: blue;">Intel’s
August 14-nm announcement</span></a>, you can find the air-gaps in the M5 level:<o:p></o:p></span><br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgKP6tC3lDP86Ox8f8XEmloMseia8T7Mgwewm3FjGmCxbGTbptelaEW8nF-xHWlDjZ9KT_mZxxSJ500fDOJQuAxZyS2lG-AduhVdn2Ax60XEuahzJON1GWFybRoQWlqTLiNmewnsubnGDTc/s1600/Intel+airgaps1.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgKP6tC3lDP86Ox8f8XEmloMseia8T7Mgwewm3FjGmCxbGTbptelaEW8nF-xHWlDjZ9KT_mZxxSJ500fDOJQuAxZyS2lG-AduhVdn2Ax60XEuahzJON1GWFybRoQWlqTLiNmewnsubnGDTc/s1600/Intel+airgaps1.png" height="191" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Air-gaps shown in Intel announcement</td></tr>
</tbody></table>
<br />
<div class="separator" style="clear: both; text-align: left;">
</div>
<div class="separator" style="clear: both; text-align: left;">
<span style="font-family: inherit;">A<span lang="EN-GB">nd we did find
them in the M5 and M7 levels, but I will leave any detailed comment until a
later blog. The IITC paper [1] speaks of using a mask step to define specific
air-gap locations, and we can confirm that masking has indeed been used to
define specific locations.</span></span></div>
<div class="separator" style="clear: both; text-align: left;">
<span lang="EN-GB"></span> </div>
<div class="separator" style="clear: both; text-align: left;">
<span lang="EN-GB">Now that we are
analysing the Intel part, it would be remiss of me not to show an early shot of
the fins, and they are clearly different from the <a href="http://electroiq.com/chipworks_real_chips_blog/2012/04/"><span style="color: blue;">22-nm variety</span></a>.
There has been an obvious reduction in the width of the fin from its initial
etched dimension, and it is tempting from this image to say that the NMOS fin
is wider than the PMOS, but again more thorough discussion will have to wait. </span></div>
<div class="separator" style="clear: both; text-align: left;">
<span lang="EN-GB"><o:p></o:p></span> </div>
<div class="separator" style="clear: both; text-align: left;">
<br /></div>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiFouxTcPIS_DS6lZygtTvCCXXpW6BE-K3_k9t113GDPXu5ZH57xEAj75SxVT28yNB6eYdMSt0Gxw_QUMEr5yyJ7jRVTKd7518VM_NXplkmBlTlIxcplnxdGkuhgl3IKTKLwqyzlMAju215/s1600/Intel+fins.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiFouxTcPIS_DS6lZygtTvCCXXpW6BE-K3_k9t113GDPXu5ZH57xEAj75SxVT28yNB6eYdMSt0Gxw_QUMEr5yyJ7jRVTKd7518VM_NXplkmBlTlIxcplnxdGkuhgl3IKTKLwqyzlMAju215/s1600/Intel+fins.png" height="297" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Linear section TEM of HKMG gate in Intel 14-nm Broadwell chip</td></tr>
</tbody></table>
<span lang="EN-GB"></span><br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">IBM’s finFET is on
SOI (of course, this <i style="mso-bidi-font-style: normal;">is</i> IBM!) and has
a “unique dual workfunction process” which allows multi-V<sub>t</sub> versions
of both NMOS and PMOS, and claims <span lang="EN-GB">sub-20 nm gate
lengths. The process also includes fifteen metal layers and the latest version
of their e-DRAM technology.</span></span></div>
<span lang="EN-GB">
</span><br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">With all the
Intel/IBM hype, I have become out of order here, because paper <b style="mso-bidi-font-weight: normal;">3.1</b> from TSMC discloses what looks like
their 16FF+ 16-nm finFET technology, advanced from the 16FF reported last year.
A 15% speed boost and 30% power reduction is claimed, or <a href="http://www.tsmc.com/english/dedicatedFoundry/technology/16nm.htm"><span style="color: blue;">40%
speed gain and 60% power saving compared to the 20-nm process</span></a>. <o:p></o:p></span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">Gossip in the
industry has it that 16FF was not advanced enough for TSMC’s customers, so they
did some transistor engineering and cranked up the performance; 16FF is not
even mentioned on the website these days, and <a href="http://electronics360.globalspec.com/article/4732/apple-tsmc-and-the-seven-customers-of-16ff"><span style="color: blue;">16FF+
is now in risk production</span></a>, with endorsements by Avago, Freescale, LG
Electronics, MediaTek, Nvidia, Renesas and Xilinx, .<o:p></o:p></span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">It will be
interesting to see if any of the dimensions have changed from the 48 nm fin
pitch and 90 nm contacted gate pitch announced last year. The metal stack is
stated to be the same as the 20-nm planar process with a 1x pitch of 64 nm.<o:p></o:p></span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">Paper <b style="mso-bidi-font-weight: normal;">3.2</b> is from Avago, discussing <b style="mso-bidi-font-weight: normal;">Analog Circuit and Device Interaction in
High-Speed SerDes Design in 16nm FinFet Process</b>, and Renesas presents <b style="mso-bidi-font-weight: normal;">3.3</b>, on 16-nm 6T SRAM macros, both
presumably TSMC’s process. <b style="mso-bidi-font-weight: normal;">3.4</b> again
looks at SRAM, but this time on STMicroelectronics’ 28-nm UTBB FDSOI process.<o:p></o:p></span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">Next up is a
couple of academic papers (<b style="mso-bidi-font-weight: normal;">3.5</b> &
<b style="mso-bidi-font-weight: normal;">3.6</b>), discussing a 28-nm integrated
RF power amplifier, and a 3D-stacked light harvester on a “epi-like Ge/Si
monolithic 3D-IC with low-power logic/NVM circuits”.<o:p></o:p></span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b style="mso-bidi-font-weight: normal;"><span lang="EN-GB">3.7</span></b><span lang="EN-GB"> and <b style="mso-bidi-font-weight: normal;">3.8</b> are the Intel and IBM papers, and <b style="mso-bidi-font-weight: normal;">3.9</b> is another late-news paper, from STMicroelectronics,
but a change of pace from the finFETs – a 55-nm SiGe BiCMOS technology this
time.<o:p></o:p></span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">And by now it’s
5pm, the end of an intense afternoon!<o:p></o:p></span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">In <b style="mso-bidi-font-weight: normal;">session 4</b>, we take a look at <a href="http://www.his.com/~iedm/program/session/s4.pdf"><b style="mso-bidi-font-weight: normal;"><span style="color: blue;">Display and Imaging Systems</span></b></a>. STMicroelectronics starts us off
discussing <b style="mso-bidi-font-weight: normal;">MOS Capacitor Deep Trench
Isolation for CMOS Image Sensors (4.1)</b> in a joint talk with CNRS and
CEA-LETI.</span></div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">One of the goals in
image sensors has to be integrating the A/D converters on each pixel, instead
of at the edge of the pixel array, and 3D stacking comes to images sensors in
paper <b style="mso-bidi-font-weight: normal;">4.2</b> from NHK and U Tokyo; in
which SOI wafers are direct bonded so as to provide each pixel with A/D
conversion.</span></div>
<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjMIwPtb4-aHqq2r2cU76oO5aHmH2VxRuPiGt6tL5hLLxM_aafITl8tXDsb5b9xC9nl6-NkVvPiE0Cvor0G7c8EVB6akdFQhgbKsRpk-eqkyj-9afaloLdK1FH-pAwWpuKPz0PM1ton44fT/s1600/Goto+4.2.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjMIwPtb4-aHqq2r2cU76oO5aHmH2VxRuPiGt6tL5hLLxM_aafITl8tXDsb5b9xC9nl6-NkVvPiE0Cvor0G7c8EVB6akdFQhgbKsRpk-eqkyj-9afaloLdK1FH-pAwWpuKPz0PM1ton44fT/s1600/Goto+4.2.png" height="90" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Conceptual diagram of
the image sensor pixel (left) and SEM cross-section bonded CMOS image
sensor pixel </td></tr>
</tbody></table>
<br />
<span lang="EN-GB">However, we won’t
be seeing this in a phone anytime soon, as it is a proof-of-concept with 60-µm
square pixels, as opposed to the 1-2 µm pixel pitch in most phone cameras.<o:p></o:p></span><br />
<br />
<span lang="EN-GB">NHK (jointly with
Panasonic and U Hyogo) has another stacked sensor in <b style="mso-bidi-font-weight: normal;">4.3</b>, this time a selenium photodiode stacked on CMOS circuitry.<o:p></o:p></span><br />
<br />
<span lang="EN-GB">The remaining four
papers are academic, covering far-infrared (<b style="mso-bidi-font-weight: normal;">4.4</b>), a stacked SOI multi-band CCD (<b style="mso-bidi-font-weight: normal;">4.5</b>), an embedded CCD in CMOS (<b style="mso-bidi-font-weight: normal;">4.6</b>),
and the display paper is <b style="mso-bidi-font-weight: normal;">4.7</b>, a
solid-state incandescent device.<o:p></o:p></span><br />
<br />
<b style="mso-bidi-font-weight: normal;"><span lang="EN-GB">Session 5</span></b><span lang="EN-GB"> covers <a href="http://www.his.com/~iedm/program/session/s5.pdf"><b style="mso-bidi-font-weight: normal;"><span style="color: blue;">Nano Device Technology – 2D Devices</span></b></a>, a research session; <b style="mso-bidi-font-weight: normal;">5.5</b> is a review of <b style="mso-bidi-font-weight: normal;">Nanophotonics with two-dimensional atomic crystals</b>; the other
papers all cover graphene devices (<b style="mso-bidi-font-weight: normal;">5.3</b>,
<b style="mso-bidi-font-weight: normal;">5.4</b> and <b style="mso-bidi-font-weight: normal;">5.6</b>), black phosphorus (5.2), and molybdenum </span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">disulphide</span><span lang="EN-US"> </span><span lang="EN-GB">and tungsten diselenide (<b style="mso-bidi-font-weight: normal;">5.1</b>, <b style="mso-bidi-font-weight: normal;">5.7</b>).<o:p></o:p></span><br />
<br />
<span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s6.pdf"><b style="mso-bidi-font-weight: normal;"><span style="color: blue;">Resistive RAM</span></b></a> is discussed in <b style="mso-bidi-font-weight: normal;">session 6</b>. CEA-Leti has three papers in the afternoon,<span style="mso-spacerun: yes;"> </span>(<b style="mso-bidi-font-weight: normal;">6.1,
6.3, 6.5</b>) The first (joint with Altis Semi) looks at oxygen vacancies in
doped oxide/Cu-based conductive bridge RAM (CBRAM), improving the Cu filament
formation in the resistive layer; <b style="mso-bidi-font-weight: normal;">6.3</b>
is an invited paper that takes a higher level view of CBRAM and OxRAM devices
in two different applications; and <b style="mso-bidi-font-weight: normal;">6.5</b>
is a detailed examination of CBRAM operation.</span><br />
<br />
Micron and Sony get together to build a 27-nm 16Gb Cu-ReRAM part in <strong>6.2</strong>, with a 1T 6F2 cell – definitely some DRAM technology showing up here, in the buried wordlines:<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhpIv-sEKaLXaTc_tI1tRYKm9S3OjJrjxptEJAEoLkt1L7r9BaBKAdz601JvJ2sCs9h2NPckkI8kU2wzWZLMVje7Ae1gXMQ8KHsCEBqGlWNfl2dY36qSkghPSwJvlfeCPRkG4xa5fmuZtPm/s1600/6.2+Zhurak.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhpIv-sEKaLXaTc_tI1tRYKm9S3OjJrjxptEJAEoLkt1L7r9BaBKAdz601JvJ2sCs9h2NPckkI8kU2wzWZLMVje7Ae1gXMQ8KHsCEBqGlWNfl2dY36qSkghPSwJvlfeCPRkG4xa5fmuZtPm/s1600/6.2+Zhurak.png" height="155" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Schematic of Micron/Sony ReRAM (left) and TEM cross-section of access devices</td></tr>
</tbody></table>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">TSMC and National
Tsing Hua U have a 28-nm BEOL RRAM in <b style="mso-bidi-font-weight: normal;">6.4</b>;
Stanford U looks at thickness limits in HfO-based RRAM in <b style="mso-bidi-font-weight: normal;">6.6</b>; Crossbar (<b style="mso-bidi-font-weight: normal;">6.7</b>)
discusses crossbar RRAM arrays; and imec/KU Leuven finishes the session with a
paper on a TiN/Si/TiN selection device for RRAM switching elements (<b style="mso-bidi-font-weight: normal;">6.8</b>).<o:p></o:p></span></div>
<br />
<span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s7.pdf"><b style="mso-bidi-font-weight: normal;"><span style="color: blue;">Modeling Simulation of Extremely Scaled Group IV and III-V FETs</span></b></a>
is the topic in <b style="mso-bidi-font-weight: normal;">session 7</b>, looking
way ahead. </span><span lang="EN-GB">In paper <b style="mso-bidi-font-weight: normal;">7.1</b>, imec and Synopsys look at the
stress effects of 3D stacking on 7-nm devices(!); <b style="mso-bidi-font-weight: normal;">7.2</b> examines mobility enhancement in sub-14nm FDSOI, by the
CEA-Leti/STMicroelectronics/IMEP/IBM/SOITEC FDSOI crew; and transient
electrothermal effects in nanoscale FETS are considered in <b style="mso-bidi-font-weight: normal;">7.3</b>., from Osaka U and Kobe U, and JST-CREST.<o:p></o:p></span><br />
<br />
<span lang="EN-GB">Victor Moroz
(Synopsys) does a comparative analysis of 7-nm finFETs in different materials
in <b style="mso-bidi-font-weight: normal;">7.4</b> – this might be a follow-up
of his <a href="http://www.avsusergroups.org/jtg_pdfs/2014_7moroz_Synopsis.pdf"><span style="color: blue;">talk
at Semicon West</span></a> back in July, in which he concluded that silicon is still
the best channel material, at least for low-power mobile devices.<o:p></o:p></span><br />
<br />
<span lang="EN-GB">Samsung and Udine
U also look at different material nFinFETs (<b style="mso-bidi-font-weight: normal;">7.5</b>, <b style="mso-bidi-font-weight: normal;">7.6</b>), and Peking U
discusses III-V ultra-thin body pMOSFETs in the last paper of the session (<b style="mso-bidi-font-weight: normal;">7.7</b>).<o:p></o:p></span><br />
<br />
<span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s8.pdf"><b style="mso-bidi-font-weight: normal;"><span style="color: blue;">NEMS (Nanoelectromechanical Systems) and Energy Harvesters</span></b></a> are
dealt with in <b style="mso-bidi-font-weight: normal;">Session 8</b> – six
academic papers, ranging from graphene and Mo disulphide atomic-scale layers
that vibrate at RF frequencies (<b style="mso-bidi-font-weight: normal;">8.1</b>),
to photoelectric hydrolysis on MIS photocathodes (<b style="mso-bidi-font-weight: normal;">8.6</b>). </span><br />
<span lang="EN-GB"></span><br />
<span lang="EN-GB"></span>For those interested in energy storage, Intel
have fabricated porous silicon capacitors (<b style="mso-bidi-font-weight: normal;">8.2</b>)
that can potentially be integrated on-die or onto solar cells, taking advantage
of the extreme conformal deposition capabilities of atomic-layer deposition
(ALD). The image below shows a top-down view of the porous silicon before and
after ALD TiN deposition; the wall of the pore walls get thicker, but the pore
structure doesn’t change. Capacitances of up to 3 milliFarads/ sqcm
are claimed.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEheaAnguVgeaGD5C57Dq9mFzDTyiPCq0HDtfFf96KY2j2t0g1L0ly7c-_Rjw2gd4u6M9QATdc2RB2elHf7jeSke8sAchLBl4NFhBOc5BvwnTn56rhXTxIuHv9gDKsdcXY375_vRjN4Pb2na/s1600/8.2+Fig+5_Gardner.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEheaAnguVgeaGD5C57Dq9mFzDTyiPCq0HDtfFf96KY2j2t0g1L0ly7c-_Rjw2gd4u6M9QATdc2RB2elHf7jeSke8sAchLBl4NFhBOc5BvwnTn56rhXTxIuHv9gDKsdcXY375_vRjN4Pb2na/s1600/8.2+Fig+5_Gardner.png" height="143" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Top-down SEM images of porous silicon capacitors before and after TiN deposition</td></tr>
</tbody></table>
Then in the evening we have the <b style="mso-bidi-font-weight: normal;">conference reception</b> at
6.30, through until 8 pm.<br />
<br />
<span lang="EN-GB"><strong>Tuesday<o:p></o:p></strong></span><br />
<br />
<span lang="EN-GB">In the morning we have
another seven parallel sessions, starting with <b style="mso-bidi-font-weight: normal;"><span style="color: black;">session 9</span></b> on <a href="http://www.his.com/~iedm/program/session/s9.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Advanced CMOS Devices for 10nm Node and Beyond</span></span></b></a></span><b><span lang="EN-US" style="mso-ansi-language: EN-US;">, </span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">so another one I will
definitely be targeting. <o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">The first paper (<b>9.1</b>, from IBM/STMicroelectronics/SOITEC/CEA-Leti)
is about strained 10-nm FDSOI devices, incorporating “a fully compressively
strained 30% SiGe-on-insulator (SGOI) channel PFET on a thin (20nm) BOX
substrate”; they also report ‘strain reversal’ in a PFET – is that so much
strain that it reduces mobility? In their workshops at last year’s IEDM and
Semicon West, CEA-Leti have been showing a roadmap that jumps from 28-nm to
14-nm and then 10-nm nodes – this looks like the first showing of the 10-nm
technology.<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">That is followed <b>(9.2)</b> by an invited
talk from Simon Deleonibus of CEA-Leti on how process technologies can move us
towards the zero-power era(?). <o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Purdue U claims the <b>First Experimental
Demonstration of Ge CMOS Circuits</b> <b>(9.3)</b> on a GeOI substrate, while
TSMC details InAlP-capped Ge nFETs on Si and Ge substrates (<b>9.4</b>), and Ge
n-finFETs on Si (<b>9.5</b>). Still in germanium, National Taiwan U talks Ge
nanowire nFETs on SOI (<b>9.6</b>).<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">The last paper of the session (9.7) is from
AIST in Japan on tunnel finFETS in a CMOS process.<o:p></o:p></span><br />
<br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;">Session 10</span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is a focus session
on </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s10.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Novel Imagers and Specialty Imaging
Applications</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">, starting with an invited talk by Jiaju Ma (<b>10.1</b>)
from the Thayer School of Engineering at Dartmouth, on the Quanta image sensor;
as near as I can make out, this type of sensor scans the pixel array so fast
that it effectively reads individual photoelectrons, and the image is formed by
integrating x, y, and time. <o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Paper <b>10.2</b>
from TU Delft discusses single-photon avalanche diodes (SPADs), which have
enabled solid state range finding, fluorescence lifetime imaging, and time-of-flight
positron emission tomography. The topic of <b>10.3</b> (Ritsumeikan U, TU
Delft, Osaka U) is high-speed image sensors, aiming for one giga-frame per
second!<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Another invited talk
is by Siemens (<b>10.4</b>), about organic photodetector imaging, and next<span style="mso-spacerun: yes;"> </span>imec details a CMOS-compatible approach to
hyper- and multispectral imaging (<b>10.5</b>).<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">In a different spin, Annette
Grot of Pacific Biosciences (<b>10.6</b>) will discuss how high-resolution,
low-noise and high-speed image sensors have enabled large amounts of DNA to be sequenced
quickly and at reduced cost; and how further advances will keep on pushing
productivity and cost reduction.<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">For the final talk,
we go from chip-scale to huge – the large scale hybrid pixel detector systems
used at the </span><span lang="EN-GB" style="font-size: 11pt;">Large Hadron
Collider </span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">experiments at CERN (<b>10.8</b>).<o:p></o:p></span><br />
<br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;">Session 11 </span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">is the second group
of talks about power and compound semi technologies, this time on </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s11.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">High Voltage and RF Devices</span></span></b></a></span><b><span lang="EN-US" style="mso-ansi-language: EN-US;">. </span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Five of the six
papers are on GaN devices, and one (<b>11.2</b>) describes a diamond MOSFET
good up to 400C. We have a new acronym in there – a SLCFET (Super-Lattice
Castellated Field Effect Transistor), with a 3D castellated gate structure (<b>11.5</b>)
– that should make for a couple of interesting slides!<o:p></o:p></span><br />
<br />
<span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s12.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Circuit/Device Variability and Integrated
Passives Performance</span></span></b></a></span><b><span lang="EN-US" style="mso-ansi-language: EN-US;"> </span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">is the focus of<b> session 12</b>; the middle papers, <b>12.3</b> and <b>12.4</b>
are the passives talks, on <b>Ultra-High-Q Air-Core Slab Inductors</b> (IBM),
and <b>Above CMOS Integrated High Quality Inductors </b>for wireless power
transmission (HONG Kong UST). The other discussions range from finFET
simulations (<b>12.1</b> and <b>12.2</b>) through MTJs for random number
generation (<b>12.5</b>), noise suppression by using dynamic threshold voltage
MOSFETs (<b>12.6</b>), and finally a consideration by ARM of poly pitch co-optimization
in standard cells below 28-nm (<b>12.7</b>).<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="color: black; mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">We look ahead to TFETs and
other </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s13.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Steep-Swing Devices</span></span></b></a></span><span lang="EN-US" style="color: black; mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> in <b>session 13. </b>The first<b> </b>paper (UCal Berkeley, Toshiba)
discusses a nano-mechanical relay (<b>13.1</b>), which inherently has zero
off-state leakage and perfectly abrupt ON/OFF switching behavior, but also
serious manufacturing challenges. <b>13.2</b> and <b>13.3</b> are TFET talks,
the <b>13.4</b> topic is a Schottky-barrier Si FinFET, and <b>13.5</b> and <b>13.6</b>
review piezoelectric negative differential capacitance effects and devices.<o:p></o:p></span><br />
<br />
<span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s14.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Advanced Memories and TSV</span></span></b></a></span><b><span lang="EN-US" style="color: black; mso-ansi-language: EN-US;"> </span></b><span lang="EN-US" style="color: black; mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">are the subjects of <b>session 14</b>; the first four papers are more
resistive RAM, from imec (<b>14.1</b> and <b>14.2</b>), Politecnico di Milano/Micron
(14.3) and Politecnico di Milano/Adesto (<b>14.4</b>). Adesto is the only
company I know actually selling </span><span lang="EN-GB"><a href="http://www.adestotech.com/cbram-family"><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"><span style="color: blue;">CBRAM parts</span></span></a></span><span lang="EN-US" style="color: black; mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">, although we haven’t had a chance to look at them yet.<o:p></o:p></span><br />
<br />
<b><span lang="EN-US" style="color: black; mso-ansi-language: EN-US;">14.5</span></b><span lang="EN-US" style="color: black; mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is a
follow-up paper looking at noise in Samsung’s V-NAND flash [2], and <b>14.6</b>
is also a follow-up from IBM on mobile ion penetration from BEOL layers close
to TSVs. IBM’s TSV process uses MEOL connection to the TSVs [3], so it’s
feasible that there could be some cross-contamination. Tohoku U contributes the
last discussion (<b>14.7</b>), testing polyimide TSV liners as a way of
reducing the stress in the adjacent silicon.<o:p></o:p></span><br />
<br />
<span lang="EN-GB">More sensors and
MEMS papers in <a href="http://www.his.com/~iedm/program/session/s15.pdf"><b style="mso-bidi-font-weight: normal;"><span style="color: blue;">session 15</span></b></a>; the first three are
from Tsinghua U, about different applications of graphene MEMS (<b style="mso-bidi-font-weight: normal;">15.2</b> also from Berkeley), and TSMC/U
Illinois contribute <b style="mso-bidi-font-weight: normal;">15.4</b>, on an
integrated 180-nm SOI-CMOS biosensor.<o:p></o:p></span><br />
<br />
<span lang="EN-GB">A*STAR in
Singapore author the final two papers, but on very different topics. <b style="mso-bidi-font-weight: normal;">15.5</b> is an optical biosensor with Ge
photodetectors built in to the back end, and <b style="mso-bidi-font-weight: normal;">15.6</b> details a MEMS-tunable laser combined with a photonic IC.<o:p></o:p></span><br />
<br />
<span lang="EN-GB">The speaker at the
<strong>conference lunch</strong> will be</span><span lang="EN-GB" style="mso-ansi-language: EN-US;">
</span><span lang="EN-US" style="mso-ansi-language: EN-US;">T.J. Rodgers, founder,
President and CEO of Cypress Semiconductor, a well-known voice in the business
for decades. Given the recent news of the merger between Cypress and Spansion,
he could be an illuminating speaker!<o:p></o:p></span><br />
<br />
<strong>Session 16</strong> focuses on <a href="http://www.his.com/~iedm/program/session/s16.pdf"><b style="mso-bidi-font-weight: normal;"><span style="color: blue; font-family: inherit;">Ge and SiGe Transistors</span></b></a><span style="font-family: inherit;">, starting with an IBM/GLOBALFOUNDRIES
report (<b style="mso-bidi-font-weight: normal;">16.1</b>) on strained SiGe-OI
finFETs with 50% Ge and fin width of 3.3 nm and gate length of ~16 nm; clearly
aimed at the 10-nm node.</span><br />
<br />
<span lang="EN-GB">Looking a bit further
into the future, CEA-Leti/STMicroelectronics/SOITEC (<b style="mso-bidi-font-weight: normal;">16.2</b>) examine omega-gate CMOS nanowires, with strained SiGe-channel
p-FETs and Si-channel n-FETs, integrated into a SOI-CMOS process. From the look
of the pictures below they are using a gate-first approach, so there is still
some life in that technology.</span><br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgCIwwz77JNVGj-2gJeLEFcT4QPoZrbPQ3glZEFimEJF5aZUhX70xLVsJiWUnO4HkOgrewagYlyRhMKnbg26QLP_YxMULOfqMB-23iXHMpkgCMKndrGFQ-j3bnBHNspfxialnkTA7vLM-kl/s1600/16.2+Fig4(combined)_Barraud-c.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgCIwwz77JNVGj-2gJeLEFcT4QPoZrbPQ3glZEFimEJF5aZUhX70xLVsJiWUnO4HkOgrewagYlyRhMKnbg26QLP_YxMULOfqMB-23iXHMpkgCMKndrGFQ-j3bnBHNspfxialnkTA7vLM-kl/s1600/16.2+Fig4(combined)_Barraud-c.jpg" height="196" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">TEM images of nanowire pFET</td></tr>
</tbody></table>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b><span lang="EN-US" style="mso-ansi-language: EN-US;">16.3</span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is another nanowire
paper from National Tsing Hua U, this time with dopant-free Ge junctionless
nanowire non-volatile memories as well as Si nanowire FETs; and <b>16.4</b> is
a study of Ge quantum-well finFETs fabricated on a 300mm bulk Si substrate,
from Penn and N. Carolina SUs with TSMC and Kurt Lesker Co.<o:p></o:p></span></div>
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Imec tries out replacement metal gates on Ge
n-finFETs with raised NiSiGe source/drains in <b>16.5</b>; AIST examines
poly-Ge-OI junctionless p- and n-finFETs, fabbed by flash annealing in <b>16.6</b>;
and Purdue U (<b>16.7</b>) reports on GeOI CMOS devices with recessed S/D.<o:p></o:p></span><br />
<b style="mso-bidi-font-weight: normal;"><span lang="EN-GB"></span></b><br />
<b style="mso-bidi-font-weight: normal;"><span lang="EN-GB">Session 17</span></b><span lang="EN-GB"> looks at <a href="http://www.his.com/~iedm/program/session/s17.pdf"><b style="mso-bidi-font-weight: normal;"><span style="color: blue;">Trapping Mechanisms in AlGaN/GaN Transistors</span></b></a>; definitely at the
academic end of the scale for me, although the last paper, <b style="mso-bidi-font-weight: normal;">CMOS-Compatible GaN-on-Si Field-Effect Transistors for High Voltage
Power Applications</b>, by TSMC, seems a bit out of place (<b style="mso-bidi-font-weight: normal;">17.6</b>).</span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"><o:p></o:p></span><br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;"></span></b><br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;">Session 18</span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is the second one on
circuit/device interaction, this time considering </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s18.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Analog and Mixed Signal Circuits</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">. Xilinx studies
the interaction between devices and analog circuits used in high-speed
transceivers in both planar and FinFet processes in <b>18.1</b>. Part of this
will be using the TSMC 16-nm finFET process, we’ll see if it adds anything to
their paper in session 3.<o:p></o:p></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Broadcom looks at mismatch in HKMG transistors
related to the layout, and finds sensitivity to top metal routing, in <b>18.2</b>.
GLOBALFOUNDRIES (<b>18.3</b>) looks at <b>Analog and I/O Scaling in 10nm SoC
Technology and Beyond</b>; is it better to take an increasing proportion of the
die for hard-to-shrink analog, or go with TSVs and multiple dies?<o:p></o:p></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">CEA-Leti has a pathfinding paper (<b>18.4</b>)
reviewing RF front-end modules (FEMs) in the light of the increasing number of
modes (GSM, WCDMA, LTE, etc) and frequency bands in mobile devices. There are
now more than 40 bands worldwide, so we see multiple FEMs in the worldphones we
take apart, and keeping costs down while enhancing capability is one of the
understated challenges in the industry. <o:p></o:p></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">There is more RF from Mediatek in <b>18.5</b>,
this time examining </span><b><span lang="EN-GB">Digitally-Intensive RF
Transceivers in Highly Scaled CMOS</span></b><span lang="EN-GB" style="mso-bidi-font-weight: bold;">; apparently, these days embedded intelligence is needed on-chip to reduce
the sensitivity of circuit performance to device characteristics. <o:p></o:p></span><br />
<span lang="EN-GB" style="mso-bidi-font-weight: bold;"></span><br />
<span lang="EN-GB" style="mso-bidi-font-weight: bold;">The last paper in the session </span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">(<b>18.6</b>) </span><span lang="EN-GB" style="mso-bidi-font-weight: bold;">is from Keio U, discussing circuit/device
interaction in the 3D context of inductive coupling between dies.<o:p></o:p></span><br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;"></span></b><br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;">Session 19</span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is the third memory
session, this time on </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s19.pdf"><b><span style="color: blue;">MRAM, DRAM and NAND</span></b></a><span style="mso-bidi-font-weight: bold;">; the first three talks are focused on
STT-MRAM, from imec </span></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">(<b>19.1</b>), Hanyang U/Samsung (<b>19.2</b>),
and LEAP (<b>19.3</b>). Then IBM updates on their embedded DRAM (<b>19.4</b>),
now at the 22-nm node in their latest Power8 processor (which, being IBM, is
~650 sq. mm!).<o:p></o:p></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">TSMC discusses a new Self-Aligned Nitride
non-volatile memory cell in <b>19.5</b>, and Macronix updates us on their
BE-SONOS charge-trapping NAND flash (<b>19.6</b>) in the last paper of the
session.<o:p></o:p></span><br />
<span lang="EN-GB"></span><br />
<span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s20.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Characterization and Reliability of Advanced
Devices</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is the subject of <b>Session 20</b>; papers <b>20.1</b>,
<b>20.3</b>, and <b>20.5 </b>all deal with nanowire characterization; imec has
two studies, on HKMG InGaAs finFETs (<b>20.2</b>), and ESD diodes in Si finFETS
(<b>20.4</b>); and finally two invited reliability presentations, by Jim
Stathis of IBM (<b>20.6</b>) and Tony Oates of TSMC (<b>20.7</b>), on what the
challenges are in their field as we move beyond 14/16 nm.<o:p></o:p></span><br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;"></span></b><br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;">Session 21</span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is a group of five
papers discussing </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s21.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Atomistic Modeling of Device Interfaces and
Materials</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">, the first being a multi-national study of hole
traps in p-MOSFETs (<b>21.1</b>); I had not realized that such traps had
similar characteristics in different oxide dielectrics, whether it be silicon
or high-k; and it appears that hydroxyl (-OH) groups could be the cause.<o:p></o:p></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">The next three talks (<b>21.2, 21.3, 21.4</b>)
are also dielectric and interface studies, as is the last, but <b>21.5</b> is
focused on HfO and HfAlO-based RRAM.<o:p></o:p></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">We go back to MEMS in </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s22.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">session 22</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">, actually
NEMS as well, as in <b>22.1</b>, which is a review of integrating NEMS with
CMOS (U Grenoble Alpes, CEA-Leti, MINATEC), and <b>22.4</b>, another CEA-Leti
talk on polySi nanowire sensors. Tsing-hua U has two papers also, <b>22.2 </b>on
a nanomechanical thermal-piezoresistive oscillator, and <b>22.3 </b>on CMOS-MEMS
Oscillators. The final two presentations are from A*STAR, about integrating RF
MEMS resonators and phononic crystals (<b>22.5</b>), and a 9 degree of freedom
capacitive sensor.<o:p></o:p></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">That brings us to the end of the afternoon,
and </span><span lang="EN-GB"><a href="http://www.appliedmaterials.com/"><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"><span style="color: blue;">Applied
Materials</span></span></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is hosting a panel on </span><span lang="EN-GB"><a href="http://www.appliedmaterials.com/company/news/press-releases/2014/12/event-advisory-semiconductor-industry-leaders-to-examine-roadmap-beyond-7nm-at-december-16-event"><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"><span style="color: blue;">"The Transistor Revolution"</span></span></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> in the Nikko Ballroom in the Nikko Hotel</span><span class="ccbntxt"><span lang="EN-GB">. In parallel <a href="http://www.coventor.com/" target="_blank">Coventor</a> is hosting an event "<em><a href="http://www.coventor.com/events/survivor-variation-in-the-3d-era/">Survivor, Variation in the 3D Era</a>" </em>in the Carmel Room, also at the Nikko Hotel. They both usually cater us
well, so once we’re sated from the hospitality we can wander back to the Hilton
for the conference evening panel:</span></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"><o:p></o:p></span><br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;"></span></b><br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;">“60 Years of IEDM and Counting: Did we push
silicon based devices for integrated electronics to the ultimate and what does
the future hold?”</span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> <o:p></o:p></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Usually there are two panels, having one
avoids conflicts this year; and there are some distinguished panelists – Krishna
Saraswat from Stanford University, with two colleagues, Yoshio Nishi and Philip
Wong, Chenming Hu (UCal Berkeley), Hiroshi Iwai Tokyo Institute of Technology),
Jesus del Alamo (MIT), and Kurt Petersen, co-founder of six MEMS companies, and
a member of the Band of Angels.</span><br />
<br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;">Wednesday<o:p></o:p></span></b><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Wednesday morning has <b>sessions 25 – 31</b>;
<b>S25</b> on </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s25.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">III-V for Logic</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">; MIT has
two papers, on InGaAs Quantum-Well MOSFETs (<b>25.1</b>), and InGaAs/InAs
heterojunction single nanowire vertical tunnel FETs (<b>25.5</b>).<span style="mso-spacerun: yes;"> </span><o:p></o:p></span><br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;"></span></b><br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;">25.2</span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is an invited review
of “<b>High-Performance III-V Devices for Future Logic Applications</b>”, by
Dae-Hyun Kim of GLOBALFOUNDRIES; <b>25.3</b>, by IBM, is more high-performance
self-aligned InGaAs-channel MOSFETs; <b>25.4</b> (UCal, Santa Barbera) is also
InGaAs, but with InP Recessed Source/Drain Spacers; and <b>25.6 </b>discusses an
InAlN/AlN/GaN triple T-shape fin-HEMT (Nanyang TU, Ohio State U, Institute of
Materials Research and Engineering).</span><span lang="EN-GB"><o:p></o:p></span><br />
<b><span lang="EN-US" style="color: black; mso-ansi-language: EN-US;"></span></b><br />
<b><span lang="EN-US" style="color: black; mso-ansi-language: EN-US;">S26</span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> covers </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s26.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Thin Film Transistors for Display
and Large Area Electronic Applications</span></span></b></a></span><b><span lang="EN-US" style="mso-ansi-language: EN-US;">.</span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> Imec demonstrates an
ultra-low power organic 8 bit transponder chip in <b><span style="color: black;">26.1</span></b><span style="color: black;">, followed by IBM with heterojunction field-effect
thin-film transistors (TFTs) with crystalline Si channels, and gate regions
comprised of hydrogenated amorphous silicon or organic materials (<b>26.2</b>).</span></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"><span style="color: black;"></span></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"><span style="color: black;">CBRITE is next up <span style="color: black;">(<b>26.3</b>)</span>, on High Performance Metal Oxide TFTs,
then a change of pace to carbon nanotubes with sputtered and spray-coated metal
oxides to form complementary inverters, from the Swiss Federal Institute of Technology,
Imperial College London, and U Würzburg (<b><span style="color: black;">26.4</span></b><span style="color: black;">).</span></span></span><br />
<br />
Believe it or not, Delft U has worked out a way to put silicon TFTs on paper or other soft substrates:<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhw4czQTfLq87t_khVrRPyuAlIwD_ljr099fPm6OyZj78fBGVwwFYNYbqXaOgpDbftJhHbP0lxIp6x5AIO1_eZ_Ktk0YO4nDL6qfIwdex_AwV0b_euIKldYZkk3Ud4GAl6kccQ17X2yqpEf/s1600/26.5+Fig+3+lSi+on+paper+large_Trifunovic.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhw4czQTfLq87t_khVrRPyuAlIwD_ljr099fPm6OyZj78fBGVwwFYNYbqXaOgpDbftJhHbP0lxIp6x5AIO1_eZ_Ktk0YO4nDL6qfIwdex_AwV0b_euIKldYZkk3Ud4GAl6kccQ17X2yqpEf/s1600/26.5+Fig+3+lSi+on+paper+large_Trifunovic.jpg" height="400" width="298" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Photograph of polysilicon thin-film transistors (the brown portion of the image) printed on paper.</td></tr>
</tbody></table>
“The Delft team made the devices by casting a quantity of liquid polysilane onto a substrate, and forming a thin film from it by “doctor-blading,” or skimming it with a blade. High-performance polysilicon channel regions then were formed by laser annealing, using short pulses of coherent light to selectively crystallize the disordered film. The maximum temperature required was only 150ºC, making the TFTs suitable for paper and plastic substrates such as PET and PEN.” (<strong>26.5</strong>)<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"></span><br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Tsing Hua U finishes up the session with the
last two papers – a study of “<b>Ultra-Thin Body (2.4nm) Poly-Si Junctionless
Thin Film Transistors with a Trench Structure</b>”, claimed to be useful for
displays and 3DICs; and more poly-Si channel junctionless<span style="mso-spacerun: yes;"> </span>FETs, but this time with a poly fin (<b>26.6,
26.7</b>).<span style="color: black;"><o:p></o:p></span></span><br />
<br />
<span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s27.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Hybrid and 3D Integration</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is the
topic of <b>Session 27</b>; TSMC<b> </b>starts off with a review paper about wafer-level
system integration technologies (<b>27.1</b>), followed by Nikon, demonstrating
their precision-aligning Cu-Cu bonding system for 3DICs (<b>27.2</b>); then
TSMC adds high-k metal-insulator-metal capacitors to their CoWoS interposers (<b>27.3</b>).</span><br />
<br />
Stanford U pushes the boundaries in paper <strong>27.4</strong> by integrating traditional silicon-FETs with RRAM and carbon nanotube-FETs, to form four vertically-stacked circuit layers (logic layer followed by two memory layers followed by a logic layer).<br />
<br />
CEA-Leti has been working on monolithic 3D integration for a while, and here they consider the thermal budget of the bottom layers (<strong>27.5</strong>). The last paper has KAIST transferring SOI silicon nanowire SONOS memory onto a plastic substrate, after thinning down to the buried oxide (<strong>27.6</strong>).<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiVKvcjpFoPqUuj-if5R6A_a9DXbgXbSXoTMZT0IqzFcp5LCVVOjQnuzPYSg3yPDXLTE8fTUbG-nyJ7G3Ao7CrTXyPO7Su7-hQTA0UdcKC6ZpBVQOcIRh-NE3cp51Mucr8eupq_ZAhrpXOJ/s1600/27.6+Fig1_Choi.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiVKvcjpFoPqUuj-if5R6A_a9DXbgXbSXoTMZT0IqzFcp5LCVVOjQnuzPYSg3yPDXLTE8fTUbG-nyJ7G3Ao7CrTXyPO7Su7-hQTA0UdcKC6ZpBVQOcIRh-NE3cp51Mucr8eupq_ZAhrpXOJ/s1600/27.6+Fig1_Choi.jpg" height="237" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">(a) shows the nanowire FETs on an SOI wafer; (b) shows the ultrathin GAA SONOS devices transferred onto a flexible substrate.</td></tr>
</tbody></table>
We have more emerging memory papers in <strong><a href="http://www.his.com/~iedm/program/session/s28.pdf" target="_blank">session 28</a></strong>, together with a couple on heterogeneous integration.
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Toshiba starts the session discussing high
density STT-MRAM for cache memory (<b>28.1</b>), using MTJs embedded in the
back-end stack. Tohoku U and NEC look at hybrid MTJ/CMOS logic in <b>28.2</b>
to make ultra-low-power logic LSI, and Rambus investigates surge current
control in RRAM arrays in <b>28.3</b>.<o:p></o:p></span></div>
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Paper <b>28.4</b> is a CEA-Leti (et al.) study
of pattern recognition using convolutional neural networks made from HfO<sub>2</sub>
based OxRAM devices as binary synapses. National Chiao Tung U is also
researching synaptic use of RRAM for neuromorphic computation in <b>28.5</b>.<o:p></o:p></span><br />
<br />
Tohoku U returns with
a 3-D stacked multicore processor module made from a 4-layer 3-D stacked
multicore processor chip and a 2-layer 3-D stacked cache memory chip (<b>28.6</b>),
and using backside TSVs to enable multichip-on-wafer 3D integration. Below is an X-ray tomograph of the TSV stacks, the processor on the left and the memory on the right:<br />
<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgBpipO8kH1yrHeIduh4Poa_cvIvliGR7d18rheTvASDRzD4Vuf1VgId-z2I7utrVst2nzt2MvhPLrfSWTw48s3WHDPabnQMo3BK3Ceuunle6X9d4IQ2pBQDu2qqxbrMa8SDQOqM5FbTqLa/s1600/28.6+Figure17_LKW_Tohoku.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgBpipO8kH1yrHeIduh4Poa_cvIvliGR7d18rheTvASDRzD4Vuf1VgId-z2I7utrVst2nzt2MvhPLrfSWTw48s3WHDPabnQMo3BK3Ceuunle6X9d4IQ2pBQDu2qqxbrMa8SDQOqM5FbTqLa/s1600/28.6+Figure17_LKW_Tohoku.jpg" height="141" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">X-ray CT scans of TSV arrays in the four-layer stacked multicore processor chip (left) and the two-layer stacked cache memory chip (right)</td></tr>
</tbody></table>
<br />
In<strong> 28.7</strong>, Penn State U et al.
demonstrate coupled hybrid vanadium dioxide FET oscillators in a platform for
associative computing, claiming ~20x power reduction compared with CMOS; and
the last paper from UCal Berkeley (<b>28.8</b>) integrates NEMS into a CMOS
back-end stack for ultra-low power applications.<o:p></o:p><br />
<br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;">Session 29</span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> continues the memory
theme, discussing </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s29.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">PCM and Neural Networks</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">, and
kicked off (<b>29.</b>1) by Micron Italy (et al.) looking into different GeSbTe
PCM cell architectures. <o:p></o:p></span><br />
<br />
<strong>29.2</strong> is from the Japanese LEAP consortium, describing a new type of PCM, “topological-switching random-access memory,” (TRAM). It differs from conventional PCM in that the latter works by the rapid heating of a chalcogenide material, which shifts it between its crystalline and amorphous states; whereas TRAM stores data by movement of germanium atoms within a GeTe/SbTe crystal superlattice:<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiRTdlW3vB9fBfn-PSNz_02bCzDkdyKr1c1QyP0SvQfFWMeiJjZrCsos_U4BGs-sNdCEmcNMmmfEbK27oY9mAgTivDSoGqni9AVpQYWWfPZgjfFbd6z9HEsUOR8ZiysW4vEOHdE9BtlWtvx/s1600/29.2+Fig1.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiRTdlW3vB9fBfn-PSNz_02bCzDkdyKr1c1QyP0SvQfFWMeiJjZrCsos_U4BGs-sNdCEmcNMmmfEbK27oY9mAgTivDSoGqni9AVpQYWWfPZgjfFbd6z9HEsUOR8ZiysW4vEOHdE9BtlWtvx/s1600/29.2+Fig1.jpg" height="196" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Comparison of phase-change random access memory (PRAM) and topological-switching random access memory (TRAM)</td></tr>
</tbody></table>
<br />
The authors claim up to 20x reduction in programming energy, achieving a set/reset current as low as 55 µA.<br />
<br />
<span lang="EN-GB">We have an invited
paper in <b style="mso-bidi-font-weight: normal;">29.3</b>,<b style="mso-bidi-font-weight: normal;"> “Phase Change Memory and its Intended Applications”</b>, by Chung Lam
of IBM, followed by a statistical study of PCM to optimize memory capacity (<b style="mso-bidi-font-weight: normal;">29.4</b>,<b style="mso-bidi-font-weight: normal;"> </b>UCal Berkeley et al.). We get back to PCM-based neural networks in
<b style="mso-bidi-font-weight: normal;">29.5</b>, again from IBM, and Politecnico
di Milano/Micron look at PCM set-transition energies (square vs triangular
pulse) in <b style="mso-bidi-font-weight: normal;">29.6</b>.<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">IBM again takes the podium in </span><b style="mso-bidi-font-weight: normal;"><span lang="EN-GB">29.7</span></b><span lang="EN-GB">, examining access devices for crossbar resistive memories, and they
are a co-author with Macronix and </span><span lang="EN-GB" style="font-size: 11pt;">National Tsing Hua U in the last paper, detailing a PCM recovery method
– apparently a local anneal can be done on-chip to recover the phase-change
properties if they degrade due to too many cycles </span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">(<b>29.</b>8)</span><span lang="EN-GB" style="font-size: 11pt;">.</span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"><o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Simulation of </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s30.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Novel Materials and Devices for FETs</span></span></b></a></span><b><span lang="EN-US" style="mso-ansi-language: EN-US;"> </span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">are considered in <b>session
30</b>; Toyota Tech Institute, Osaka U, and U Tsukuba (<b>30.1</b>)</span><span lang="EN-US" style="font-size: 11pt;"> </span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">show that random dopant fluctuation in the source
region causes a noticeable variability in the on-current of Si nanowire
transistors, and its impact is found to be much larger than that of random
telegraph noise (RTN). <o:p></o:p></span><br />
<br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;">30.2</span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is a review of
Tunnel-FETs for future low-power technology nodes, by imec; <b>30.3 </b>(U
Florida) simulates Mo-disulphide-WTelluride vertical tunneling transistors; <b>30.4</b>
(ETH Zurich) is another Mo-disulphide transistor study, as is <b>30.5</b>, but
also evaluates W-diselenide (UCal Santa Barbara); and the session finishes with
a simulation of a (B-N) co-doped graphene TFET by Hong Kong UST/</span><span lang="EN-GB" style="font-size: 11pt;">NanoAcademic Technologies </span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">(<b>30.6</b>)</span><span lang="EN-GB" style="font-size: 11pt;">.</span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"><o:p></o:p></span><br />
<br />
The last focus session is <strong>session 31, <a href="http://www.his.com/~iedm/program/session/s31.pdf" target="_blank">Sensors, MEMS, and BioMEMS</a></strong>. It opens with a display of bio-MEMS for handling single molecules, including silicon nano tweezers, arrays of micro chambers, and chips with linear bio molecular motors (<strong>31.1</strong>, U Tokyo). The specific application is the use of MEMS technology on the molecular scale to conduct studies of DNA degradation and protein mutation related to Alzheimer’s disease. MEMS tweezers were used to trap bundles of DNA molecules to study them for stiffness and viscosity, which are markers of DNA degradation. Here we have an electron microscope image of a DNA molecular bundle between the tips:<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhyUVx4lT5VFTSSGfrtN5SGW-G4s_PCNXY6Vxnzx_Q_xcJR-2IkPOvvaNfWt0VmzegVldPD3FgRYtneG-CysRFOAhJs3arDrtPNkxcxrUVm-A4kfI1dz6Yax5NhyiiZwGPlrUogzab7uCTj/s1600/31.1+fig2_Fujita.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhyUVx4lT5VFTSSGfrtN5SGW-G4s_PCNXY6Vxnzx_Q_xcJR-2IkPOvvaNfWt0VmzegVldPD3FgRYtneG-CysRFOAhJs3arDrtPNkxcxrUVm-A4kfI1dz6Yax5NhyiiZwGPlrUogzab7uCTj/s1600/31.1+fig2_Fujita.jpg" height="302" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">DNA bundle held by MEMS tweezers</td></tr>
</tbody></table>
Next up, U Bologna/U Southampton research the use of AC nanowire sensing that can capture both magnitude and phase information of the device response (<strong>31.2</strong>); <strong>31.3</strong> is a review of “MEMS for Cell Mechanobiology” (Stanford U); and <strong>31.4</strong> is also a review, of “Organic Electrochemical Transistors for BioMEMS Applications”, from Ecole Nationale Supérieure des Mines.<br />
<span style="mso-ansi-language: EN-CA; mso-bidi-font-weight: bold;"></span><br />
<span style="mso-ansi-language: EN-CA; mso-bidi-font-weight: bold;">U Cincinnati (et al.) follows, with a
tempting look at a “novel multimodality lab-on-a-tube smart catheter”, which
can accurately track multiple parameters in an injured brain </span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">(<b>31.5</b>);
<b>31.6 (</b></span><span lang="EN-GB" style="font-size: 11pt;">Ritsumeikan U) </span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">shows off
another medical device, an </span><span style="mso-ansi-language: EN-CA; mso-bidi-font-weight: bold;">all polymer pneumatic balloon actuator, fabricated
from polymers such as polyimide and polydimethylsiloxane that we are familiar
with in the chip business. Paper <b>31.7</b> from MC10 completes the session by
demonstrating examples of skin-based systems that incorporate physiological
sensors and actuators configured in stretchable formats.<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">After the morning sessions, the </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/general/ent-lunch-writeup-14.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">IEDM Entrepreneurs Lunch</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is back
for a third year, </span><span lang="EN-GB" style="mso-bidi-font-weight: bold;">featuring
a presentation by Kathryn Kranen, Former President and CEO of Jasper Design
Automation</span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">.<o:p></o:p></span><br />
<br />
<span lang="EN-GB">Also at lunchtime
ASM is hosting their regular IEDM seminar (Wednesday this year, instead of the
Monday as of last year) on “<b style="mso-bidi-font-weight: normal;">14nm & Beyond
- Fins all Around”</b>, at the Nikko Hotel across the street from the Hilton.
There’s no website, so interested parties should contact Rosanne de Vries, by
replying to <a href="mailto:rosanne.de.vries@asm.com?Subject=Invitation:%20IEDM%20SF%202014"><span style="color: blue;">rosanne.de.vries@asm.com</span></a>.
And there’s a bit of self-promotion here, since I’m one of the guest speakers!<o:p></o:p></span><br />
<br />
We are back to <strong><a href="http://www.his.com/~iedm/program/session/s32.pdf" target="_blank">Process and Manufacturing Technology</a></strong> in <strong>S32</strong> after lunch, with a focus on Advanced Process Modules. IBM details some of its work on finFETs formed by Directed Self Assembly (DSA) in <strong>32.1</strong>, achieving 29 nm fin pitch, and maybe giving us more evidence that EUV may never happen..<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhG67h1AujT6G6gnRF16ag7l8phBiVh21aXD8fRw9BMtgTZJ9FhHPMSNC_f6u4e9Ne0I-QgYboqYRJ5NoMG5A-sll2oN6ULYSQUjZlPF9LhyAPji4dgxtoLSN3SCyJ92pbdxDr432O8FryH/s1600/32.1+FIG6-HR_Tsai.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhG67h1AujT6G6gnRF16ag7l8phBiVh21aXD8fRw9BMtgTZJ9FhHPMSNC_f6u4e9Ne0I-QgYboqYRJ5NoMG5A-sll2oN6ULYSQUjZlPF9LhyAPji4dgxtoLSN3SCyJ92pbdxDr432O8FryH/s1600/32.1+FIG6-HR_Tsai.jpg" height="296" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Fins formed by DSA with 29-nm pitch</td></tr>
</tbody></table>
In <strong>32.2</strong> Samsung discusses their 10-nm interconnect strategy; judging by the abstract, we might be moving to Cu+Ru liner by the time we get to 10 nm. An imec/Micron/Hynix joint paper (<strong>32.3</strong>) reveals a new front-end scheme (gate and diffusion replacement), which allows high-thermal budget processes for applications such as control logic for memory (e.g. DRAM periphery).<br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Paper <b>32.4</b> is from Albany CNSE and its
sponsors, examining the contact resistivity on n+ InGaAs fin sidewall surfaces;
U Tokyo discusses oxygen effects in Ge MOSFETs in <b>32.5</b>; <b>32.6</b> is a
review of ion implantation techniques and capabilities by Applied Materials,
from doping to materials engineering; and <b>32.7</b> covers “</span><b><span style="mso-ansi-language: EN-CA;">A Novel Junctionless FinFET Structure with
Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave
Annealing”</span></b><span style="mso-ansi-language: EN-CA; mso-bidi-font-weight: bold;">. The lead authors are from National Nano Device Laboratories, </span><span lang="EN-GB">National Chiao Tung U, and National Cheng Kung U, but Michael Current
and Evans Analytical are also involved, so at the least there should be some
interesting analytical data included.</span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"><o:p></o:p></span><br />
<br />
<b><span lang="EN-US" style="mso-ansi-language: EN-US;">Session 33 </span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">has </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s33.pdf"><b><span lang="EN-CA" style="mso-ansi-language: EN-CA;"><span style="color: blue;">Exploratory Devices</span></span></b></a></span><b><span style="mso-ansi-language: EN-CA;"> </span></b><span style="mso-ansi-language: EN-CA; mso-bidi-font-weight: bold;">as the subject, inevitably academic in nature
– Carnegie Mellon starts off </span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">(<b>33.1</b>)</span><span style="mso-ansi-language: EN-CA; mso-bidi-font-weight: bold;"> showing a four-terminal spintronic device,
followed by Tohoku U, investigating 1x-nm perpendicular-anisotropy CoFeB-MgO based
MTJs </span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">(<b>33.2</b>). Then we have a two-sided graphene oxide doped silicon
oxide based RRAM (<b>33.3</b>)</span><span lang="EN-US" style="mso-ansi-language: EN-CA; mso-bidi-font-weight: bold;"> </span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">from National Sun Yat-Sen U, Peking U, and Stanford
U; and a new material raises its head in (<b>33.4</b>) – iodostannane,
basically tin activated with iodine, in a new kind of transistor, the
topological-insulator field-effect transistor.<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">National Nano Device Laboratories, et al.,
present CMOS-compatible Mo-disulphide 3DFETs in <b>33.5</b>, and Stanford U end
the session with a review of carbon nanotube transistors.<o:p></o:p></span><br />
<br />
<span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s34.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Reliability: BTI, HCI and Breakdown</span></span></b></a></span><b><span lang="EN-US" style="mso-ansi-language: EN-US;"> </span></b><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">are dealt with in <b>session
34</b>. A SMIC-sponsored work on NBTI in HKMG is covered in <b>34.1</b>,
co-authored by Peking U, Liverpool John Moores U, and UCal Berkeley. Liverpool
John Moores U and imec look at NBTI of Ge pMOSFETs (<b>34.2</b>), and AIST has
researched PBTI in n-fin-TFETs in <b>34.3</b>; imec is back in <b>34.4</b>,
reviewing BTI reliability in “beyond-silicon devices”; and <b>34.5</b> covers
RTN in both SiON and HKMG devices, by Peking U and SMIC.<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Samsung (<b>34.6</b>) studies hot carrier induced
dynamic variation in nano-scaled SiON/Poly, HK/MG and finFET devices, and the
final paper of the session is from IBM and SRDC, discussing breakdown
mechanisms in dielectric BEOL stacks (<b>34.7</b>).<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">The last session (numerically), <b>session 35</b>,
covers </span><span lang="EN-GB"><a href="http://www.his.com/~iedm/program/session/s35.pdf"><b><span lang="EN-US" style="mso-ansi-language: EN-US;"><span style="color: blue;">Compact Modeling</span></span></b></a></span><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> of
devices. MIT and Purdue U get together to present a new model for FETs, which
uses only a few physical parameters and is consistent with the virtual source
model (<b>35.1</b>). They demonstrate its accuracy by comparison with measured
data for III-V HEMTs and ETSOI Si MOSFETs.<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">NXP/UFRGS have a new noise (RTN/LFN) model for
MOSFETS in <b>35.2</b>, followed by IBM discussing several width dependent transistor
current characteristics (<b>35.3</b>). We jump to TSVs in <b>35.4</b>, with a
CEA-Leti (et al.) study of thermal dissipation in 3D ICs and an associated
model; IMECAS presents a surface potential-based compact model for a-IGZO TFTs
in RFID applications in <b>35.5</b>; and Purdue U/GLOBALFOUNDRIES model MTJs in
<b>35.6</b>.<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Chronologically the last papers are due at
4.05 pm – by then a lot of attendees will have headed for home, especially
since this year’s conference is so close to the Christmas break. <o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">I will definitely be suffering from
information overload and becoming brain-numb, but with 218 papers and an
average of six parallel sessions at any one time, plus the offsite events,
that’s not really surprising. On the other hand, where else do we go to get all
this amazing stuff?<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Time to unwind, maybe do a little holiday
shopping, and go for an indulgent meal.<o:p></o:p></span><br />
<br />
<span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">References:<o:p></o:p></span><br />
<ol>
<li>
<!--[endif]--><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">H.J. Yoo et al., “<i style="mso-bidi-font-style: normal;">Demonstration of a reliable high-performance and yielding Air gap interconnect process</i>”, IITC 2010, pp. 1-3 <o:p></o:p></span></li>
<li><!--[endif]--><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">J. Jang, et al., “<i style="mso-bidi-font-style: normal;">Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High density NAND Flash Memory</i>” VLSI 2009, pp.192-193<o:p></o:p></span></li>
<li><!--[endif]--><span lang="EN-US" style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">M. G. Farooq et al., “<i style="mso-bidi-font-style: normal;">3D Copper TSV Integration, Testing and Reliability</i>”, IEDM 2011, pp.143-146<o:p></o:p></span></li>
</ol>
Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.comtag:blogger.com,1999:blog-5488132572864585098.post-50454092740351861072014-10-27T14:37:00.000-04:002014-10-27T14:43:36.396-04:00Intel's 14nm Finally Arrives!<span style="font-family: Calibri;">Early last week a couple of laptops
arrived from Japan using the Core M version of Intel’s Broadwell processor.
Straight into the lab, and within a few hours the first sight of the die
structure, confirming that it is indeed the 14-nm technology. <o:p></o:p></span><br />
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: Calibri;">This is an image of a die that was given
a bevel polish, so that we can look at the transistors in plan view:</span><br />
<span style="font-family: Calibri;"></span> </div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgRksIweLXeQ5Efwc7gAryhCnjqXzOcArZEV2xwMV_RT-Xm4BnOC_z_z-DnKUiehjj6V3jTRU0f6q0fn95xM9mwg0NxkQnjFJBute4c79m_dTwTdcMW1MNrW-BrBRX06hc5GpwBRUAFH7Lw/s1600/header21.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgRksIweLXeQ5Efwc7gAryhCnjqXzOcArZEV2xwMV_RT-Xm4BnOC_z_z-DnKUiehjj6V3jTRU0f6q0fn95xM9mwg0NxkQnjFJBute4c79m_dTwTdcMW1MNrW-BrBRX06hc5GpwBRUAFH7Lw/s1600/header21.jpg" height="206" width="320" /></a></div>
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</div>
<span style="font-family: Calibri;">It’s a bit fuzzy, due to the high
magnification, and construction we have going on next door; but we have
measured ten contacted gate pitches as you can see, and that looks pretty close
to the 70 nm that was <a href="http://files.shareholder.com/downloads/INTC/3570266827x0x775635/ae87f50f-2f66-4ab7-b35f-bd98ab44b43f/Intel_14nm_Aug11.pdf"><span style="color: blue;">announced
by Intel back in August</span></a>.<o:p></o:p></span><br />
<span style="font-family: Calibri;">
</span><div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="font-family: Calibri;"><span style="font-family: Times New Roman;">
</span></span><br />
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<span style="font-family: Calibri;"><span style="font-family: Times New Roman;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjo6SVRhAJPuLY6IGEXzOe8seHITjtqfpVEpR7bNjhjlVd5K459wXZE4r8fHwBkWykuQfrzY00xh8KE4UXCFZgUqK0C6D9Ebi0D_UqmjI57xqlgy8uB3b0NkUOz_JMPhs6GAoMRkBoQP_Ph/s1600/Intel+Aug+11_14+slide+16.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjo6SVRhAJPuLY6IGEXzOe8seHITjtqfpVEpR7bNjhjlVd5K459wXZE4r8fHwBkWykuQfrzY00xh8KE4UXCFZgUqK0C6D9Ebi0D_UqmjI57xqlgy8uB3b0NkUOz_JMPhs6GAoMRkBoQP_Ph/s1600/Intel+Aug+11_14+slide+16.png" height="180" width="320" /></a></span></span></div>
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<span style="font-family: Calibri;"> </span></div>
</div>
<span style="font-family: Calibri;">
</span><br />
<div class="separator" style="clear: both; text-align: left;">
<span style="font-family: Calibri;">On another part of the bevel we can see
the fins, and here we have counted 20 pitches:</span></div>
<div class="separator" style="clear: both; text-align: left;">
<span style="font-family: Calibri;"><o:p></o:p></span> </div>
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
</div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh0hqUlPhqDmOIyxjvQctyW80tmzh1EpmMLAA8Aqw2l_t1_7M2Z9QpLJS7F9b_janK-m1A9dcoaNoet1jatbr77E6idjUl5LfYbVLGIGmlYpdXUQVe2H-5J8O5dVG1SWgyMuoskT48hnvSY/s1600/032.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh0hqUlPhqDmOIyxjvQctyW80tmzh1EpmMLAA8Aqw2l_t1_7M2Z9QpLJS7F9b_janK-m1A9dcoaNoet1jatbr77E6idjUl5LfYbVLGIGmlYpdXUQVe2H-5J8O5dVG1SWgyMuoskT48hnvSY/s1600/032.jpg" height="320" width="320" /></a></div>
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<span style="font-family: Calibri;"></span> </div>
<div class="separator" style="clear: both; margin: 6pt 0in 0pt; text-align: left;">
<span style="font-family: Calibri;">Which agrees with the 42-nm pitch in the
Intel webcast. So far, so good!<o:p></o:p></span></div>
<div class="separator" style="clear: both; margin: 6pt 0in 0pt; text-align: left;">
<span style="font-family: Calibri;">If we look at the cross-section, Intel
has stayed with their thick top metal that they have been using since the 65-nm
node, which means that we have to squint awfully hard to see THIRTEEN layers of
metal, and a MIM-cap layer under the top metal.<o:p></o:p></span></div>
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<span style="font-family: "Calibri","sans-serif"; font-size: 11pt; line-height: 115%; mso-ansi-language: EN-CA; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;">A
look at the edge seal, which doesn’t have the top metal or the MIM-cap, makes
it easier to count twelve layers:</span></div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhEIPldGEKZdFX0SArkNgpDvT9YbGDMoNeHdvTdA6ORfrs-vz_DV3HXGpzdZH58UH1-xVA3lFPmKmcWkAPjjHRNF_gTDfznm4Vhf5gYUtmH1iEZkemVXyOzelMPiDJtty447iTQNRGJqgym/s1600/06_Inner_Die_Seal_168232-c-a_branded.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhEIPldGEKZdFX0SArkNgpDvT9YbGDMoNeHdvTdA6ORfrs-vz_DV3HXGpzdZH58UH1-xVA3lFPmKmcWkAPjjHRNF_gTDfznm4Vhf5gYUtmH1iEZkemVXyOzelMPiDJtty447iTQNRGJqgym/s1600/06_Inner_Die_Seal_168232-c-a_branded.png" height="259" width="320" /></a></div>
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<span style="font-family: Calibri;">We are used to seeing twelve-plus metal
layers in IBM chips (their 22-nm Power8 has fifteen!), but Intel has been using
nine for the last few generations, going up to eleven in the Baytrail SoC chip.</span></div>
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<span style="font-family: Calibri;">Intel quoted 52 nm interconnect pitch,
but we see 54 nm:</span></div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg3YtOLdZZZm68d_w4iCTloseo-sx69-N2-l-XgIqXbMV8ab3aYNFNz0mtSttTCxiOYpwyW1yIr__x8oCpx8Bl8cy5i6gg_LLIgov5EZWxLtYcopHws4Ha5iYTiWXMFq381US19gtE42-Ds/s1600/062.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg3YtOLdZZZm68d_w4iCTloseo-sx69-N2-l-XgIqXbMV8ab3aYNFNz0mtSttTCxiOYpwyW1yIr__x8oCpx8Bl8cy5i6gg_LLIgov5EZWxLtYcopHws4Ha5iYTiWXMFq381US19gtE42-Ds/s1600/062.jpg" height="320" width="320" /></a></div>
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<span style="font-family: Calibri;"><o:p><span style="font-family: "Calibri","sans-serif"; font-size: 11pt; line-height: 115%; mso-ansi-language: EN-CA; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;">Although
that is within measurement error, and we may not have sectioned the most
tightly packed part of the die.</span></o:p></span></div>
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<span style="font-family: Calibri;"><o:p><span style="font-family: "Calibri","sans-serif"; font-size: 11pt; line-height: 115%; mso-ansi-language: EN-CA; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;"><span style="font-family: "Calibri","sans-serif"; font-size: 11pt; line-height: 115%; mso-ansi-language: EN-CA; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;">As
yet we don’t have any detailed TEM imaging to look at the transistors or fins
in close-up, so we can’t verify if the fins have vertical walls or not, as
shown by Intel.</span></span></o:p></span></div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgJatTu8_9MncMA1Q-Gz9UteoOJiPavEbjS1r7PoEAUWBzCpTXNZwp6QcfMqkzfnlrybysM48pzqjPdHmyNG396Dx4yXWAcJEagq0zV0THShPtqxT4E88eyhjWqvdM9c3DEKUZjOAQihFa3/s1600/Intel+Aug+11_14+slide+22.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgJatTu8_9MncMA1Q-Gz9UteoOJiPavEbjS1r7PoEAUWBzCpTXNZwp6QcfMqkzfnlrybysM48pzqjPdHmyNG396Dx4yXWAcJEagq0zV0THShPtqxT4E88eyhjWqvdM9c3DEKUZjOAQihFa3/s1600/Intel+Aug+11_14+slide+22.png" height="320" width="304" /></a></div>
<span style="font-family: Calibri;"><o:p><span style="font-family: "Calibri","sans-serif"; font-size: 11pt; line-height: 115%; mso-ansi-language: EN-CA; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;"><span style="font-family: "Calibri","sans-serif"; font-size: 11pt; line-height: 115%; mso-ansi-language: EN-CA; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;"></span></span></o:p></span><br />
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<span style="font-family: Calibri;"><span style="font-family: "Calibri","sans-serif"; font-size: 11pt; line-height: 115%; mso-ansi-language: EN-CA; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;"><span style="font-family: "Calibri","sans-serif"; font-size: 11pt; line-height: 115%; mso-ansi-language: EN-CA; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;">The cross-section seems to show that
essentially the 14-nm process is a shrink of the 22-nm technology, with the modified
fins; the gate metallisation looks similar to the 22-nm, with tungsten gate
fill as in the earlier process. (As an aside, this will make it the fourth
generation replacement metal gate process – this technology has legs!)<o:p></o:p></span></span></span></div>
<span style="font-family: Calibri;"><span style="font-family: "Calibri","sans-serif"; font-size: 11pt; line-height: 115%; mso-ansi-language: EN-CA; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;"><span style="font-family: "Calibri","sans-serif"; font-size: 11pt; line-height: 115%; mso-ansi-language: EN-CA; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;">
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<span style="font-family: Calibri;"><span style="font-family: "Calibri","sans-serif"; font-size: 11pt; line-height: 115%; mso-ansi-language: EN-CA; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;"><span style="font-family: "Calibri","sans-serif"; font-size: 11pt; line-height: 115%; mso-ansi-language: EN-CA; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;"><span style="font-family: Times New Roman; font-size: small;">
</span></span></span></span></div>
<span style="font-family: Calibri;"><span style="font-family: "Calibri","sans-serif"; font-size: 11pt; line-height: 115%; mso-ansi-language: EN-CA; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;"><span style="font-family: "Calibri","sans-serif"; font-size: 11pt; line-height: 115%; mso-ansi-language: EN-CA; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;">
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<a href="http://electroiq.com/blog/2014/10/intel-and-ibm-lay-out-14nm-finfet-strategies-on-competing-substrates-at-iedm-2014/"><span style="color: blue;">Intel
and IBM are giving late news papers at IEDM</span></a> in December, and apparently there
are air gaps in the back-end dielectric stack – we have not found those yet. We
have confirmed the SRAM cell size in the cache memory is ~0.058 sq. µm.<o:p></o:p></div>
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Our analysis is ongoing, and we look
forward to some great images! And as always, we will be doing a <a href="http://ww2.chipworks.com/l/4202/2014-10-21/d9lc5/4202/156638/Chipworks_Intel_14_nm_FinFET_Reports___Product_Brief.pdf" target="_blank">bunch of reports</a>..<o:p></o:p></div>
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Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-73215867240293498612014-08-03T19:40:00.000-04:002014-08-04T09:24:46.602-04:00The Second Shoe Drops - Now We Have the Samsung V-NAND Flash<br />
Two weeks ago we posted about the TSMC 20-nm product that we had in-house; now after waiting for a year since <a href="http://www.samsung.com/global/business/semiconductor/news-events/press-releases/detail?cateSearchParam=&searchTextParam=&startYyyyParam=&startMmParam=&endYyyyParam=&endMmParam=&newsId=12990&page=3&searchType=&rdoPeriod=A" target="_blank">Samsung's announcement of V-NAND production</a>, we have that in the lab and can start to see what it looks like.<br />
<br />
The vertical flash was first <a href="http://www.samsung.com/global/business/semiconductor/news-events/press-releases/detail?cateSearchParam=&searchTextParam=&startYyyyParam=&startMmParam=&endYyyyParam=&endMmParam=&newsId=12993&page=3&searchType=&rdoPeriod=A" target="_blank">released in an enterprise solid-state drive</a> (SSD) last year, in 960 GB and 480 GB versions, but with no model number, so essentially for sampling only to established customers. Then in May this year they announced a second-generation V-NAND SSD, with a stack of 32 cell layers.<br />
<br />
However, on July 1 at this year's Samsung SSD Global Summit they <a href="http://www.samsung.com/global/business/semiconductor/news-events/press-releases/detail?cateSearchParam=&searchTextParam=&startYyyyParam=&startMmParam=&endYyyyParam=&endMmParam=&newsId=13541&page=&searchType=&rdoPeriod=A" target="_blank">unveiled the SSD 850 Pro</a>, aimed at high-end PCs and workstations, and said to be available in July. Of course we immediately put out feelers and got some on pre-order. They showed up last week and we have the first few images.<br />
<br />
First, though, let's think about what the changes are from the conventional planar NAND. Samsung posted a slick <a href="http://www.youtube.com/watch?v=21gYQcxTLe0" target="_blank">video</a> which gives a summary of the technology. The first thing to note is that we have gone from the ETOX floating-gate charge storage that we have seen in the last umpteen generations of flash, to charge-trap storage (CTF - Charge Trap Flash) in which the charge is stored on a silicon nitride layer (otherwise known as a SONOS cell - Si/SiO/SiN/SiO/Si).<br />
<br />
The SONOS stack is then oriented vertically, using a polysilicon cylinder as the substrate silicon, and wrapping the other layers around the central cylinder.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiRb8_js7qyRY7J_O96mshLgzph6c9j1X_DFShkCokxtuAl_VZkYHTewtv5CFHpdca6NN-dt62eQeqYLglZRrHEiRTeUFYvsIkSqNS8_POJuzGrt1DhXILT5hjQ3EYda5tgMu5jVqclniSy/s1600/05a.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiRb8_js7qyRY7J_O96mshLgzph6c9j1X_DFShkCokxtuAl_VZkYHTewtv5CFHpdca6NN-dt62eQeqYLglZRrHEiRTeUFYvsIkSqNS8_POJuzGrt1DhXILT5hjQ3EYda5tgMu5jVqclniSy/s1600/05a.png" height="160" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span class="Apple-style-span" style="font-size: small;">Fig. 1 Cell structure transition from planar to V-NAND stack</span></td></tr>
</tbody></table>
<br />
The wordlines (control gates) become a horizontal layer, and the bitlines are connected to the top of the polySi cylinder; the select gates are formed by the top and bottom conductive layers [1]. Samsung describes the use of a tungsten replacement metal gate [1], and 24 wordline layers plus 2 dummy wordlines and two select gates for a total of 28 layers [2].<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgbX8Q07gx52ovTst0i02EgLl0m7jZa79vYr38iSZmtSxq19e4SuMXsfezT8S8pepQs9mAoy364XD1aZUzUW_E9dc6uGfjX98s9TmwGC-8T3ofPyZYvB4tLflMjpGcwRxwpYDrHhkdpD1gH/s1600/Capture+5a.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgbX8Q07gx52ovTst0i02EgLl0m7jZa79vYr38iSZmtSxq19e4SuMXsfezT8S8pepQs9mAoy364XD1aZUzUW_E9dc6uGfjX98s9TmwGC-8T3ofPyZYvB4tLflMjpGcwRxwpYDrHhkdpD1gH/s1600/Capture+5a.png" height="400" width="321" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span class="Apple-style-span" style="font-size: small;">Fig. 2 Schematic of V-NAND cell stack</span></td></tr>
</tbody></table>
<br />
We also see in Fig.2 a "blocking layer" in between the metal gate and the SiN, which at least implies the use of a high-k dielectric instead of an oxide layer for the capacitative coupling layer, as used in their CTF parts from 2006.<br />
<br />
One of the many challenges using a vertical stack such as the V-NAND is etching through a stack of many dissimilar layers, to etch the holes for the polySi cylinder channels, the slots through the stack to separate the wordlines, and the vias down to the wordlines (etching holes down to a staircase of extended wordlines). In fact, the whole stack is a big etching problem - see Fig.3.<br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgqCZbkN8k68baHhzPeZztHe-_D_KtbJUVQEk8QaAp-fEJsW4LF6yAfa20o8wVYOpxF3vY55GvMmwWMBg4gNhIOTuEE4hfXfyoOc0NF4LNqM5LPEdeIny9SRVqPiz3CeVbd2SiNz84LYiIh/s1600/NAND-staircase-AMAT-a.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgqCZbkN8k68baHhzPeZztHe-_D_KtbJUVQEk8QaAp-fEJsW4LF6yAfa20o8wVYOpxF3vY55GvMmwWMBg4gNhIOTuEE4hfXfyoOc0NF4LNqM5LPEdeIny9SRVqPiz3CeVbd2SiNz84LYiIh/s1600/NAND-staircase-AMAT-a.png" height="307" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span class="Apple-style-span" style="font-size: small;">Fig. 3 Schematic of etching steps in V-NAND stack</span></td></tr>
</tbody></table>
<br />
Now that we have the production part, Samsung have clearly solved those problems. Let's take a first look at what's inside. Fig. 4 is a photo of the die, and Fig. 5 shows the die mark - the "A" on the end denoting the second-generation product. Interestingly, the "DG" in the part number normally denotes a 128-Gb die, but this part is actually ~86 Gb, since we have twelve flash dies in our 128-GB solid-state drive.<br />
<br />
The part described in the ISSCC paper [2] was an actual 128-Gb device, with a chip size of ~133 sq. mm. Our 86-Gb die has shrunk to ~85 sq.mm., slightly increasing the bit density from 0.96 to 0.99 Gb/sq.mm.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi47XrSFCaqiUBytUJ7xxUryzPy2HL5IG2yFrp6EdqATAUylnRBt6dJqGNefA8YYtlf9z0rT6NXHPLp3jVqtK8ImGIzMLG66eU3-7LEtlum2CokxB1YbP27qAP-jaufbcQO4LGYHN5pteay/s1600/K9HQGY8S5M-CCK0_K9ADGD8S0A_164218_oriented-r_branded.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi47XrSFCaqiUBytUJ7xxUryzPy2HL5IG2yFrp6EdqATAUylnRBt6dJqGNefA8YYtlf9z0rT6NXHPLp3jVqtK8ImGIzMLG66eU3-7LEtlum2CokxB1YbP27qAP-jaufbcQO4LGYHN5pteay/s1600/K9HQGY8S5M-CCK0_K9ADGD8S0A_164218_oriented-r_branded.png" height="217" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span class="Apple-style-span" style="font-size: small;">Fig.4 Die photo of Samsung K9ADGD8S0A V-NAND flash device</span></td></tr>
</tbody></table>
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjlFX29-g5nRcwJ3EICUMWKMuUQx3Wt_BN_H9yHQ_ZeBu_GWoG8JlWiPmYX2wEKcwH0SAL5t0dW4HQ-JF3XpYfEODSgPQvYJL023HjEUEF5ujbtkCRnKA6vtaGYfbvlhc2vLN7LbpokrbZP/s1600/K9HQGY8S5M-CCK0_K9ADGD8S0A_164218_diemrk-c_branded.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjlFX29-g5nRcwJ3EICUMWKMuUQx3Wt_BN_H9yHQ_ZeBu_GWoG8JlWiPmYX2wEKcwH0SAL5t0dW4HQ-JF3XpYfEODSgPQvYJL023HjEUEF5ujbtkCRnKA6vtaGYfbvlhc2vLN7LbpokrbZP/s1600/K9HQGY8S5M-CCK0_K9ADGD8S0A_164218_diemrk-c_branded.png" height="240" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span class="Apple-style-span" style="font-size: small;">Fig. 5 Die mark</span></td></tr>
</tbody></table>
<br />
When we cross-section the chip, the staircase shown in Fig. 3 shows up nicely:<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhDKlqfLZwyDSgPC74BPqmAPaQDJycyzaQXYEq5cxVg9aGoGDwZRFwrk1bk_qKFbi8wQqBa08CGC9D0e7_KmW0UTwA-zzB7mE7wVYplyNG3AzaBnTaf9JvMaLSe73jzXK71odf0UO28j8ma/s1600/351_Edge_Of_Array_164268-c_branded.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhDKlqfLZwyDSgPC74BPqmAPaQDJycyzaQXYEq5cxVg9aGoGDwZRFwrk1bk_qKFbi8wQqBa08CGC9D0e7_KmW0UTwA-zzB7mE7wVYplyNG3AzaBnTaf9JvMaLSe73jzXK71odf0UO28j8ma/s1600/351_Edge_Of_Array_164268-c_branded.png" height="93" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span class="Apple-style-span" style="font-size: small;">Fig. 6 SEM cross-section of Samsung V-NAND stack</span></td></tr>
</tbody></table>
<br />
In this first shot, we don't appear to have sectioned through any of the vias to the wordline layers; the vertical features appear to be polySi cylinders drilled into the outer edges of the stack. If we look closer at the edge of the array, that does appear to be the case (Fig. 7).<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEikEQYMzNhwTstUyNszNqb6VTho_VYmhbfb_dYRbcAVYT9Pyr86KfX9d88yTbZ6AyoC81DubHUxZusGvPsxcpzCA4J-F20uaia8cpYqzKJdCsNonCH_W8cbns1CINRm6oiu1Fifpk16t41K/s1600/352_Edge_Of_Array_164268-c_branded.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEikEQYMzNhwTstUyNszNqb6VTho_VYmhbfb_dYRbcAVYT9Pyr86KfX9d88yTbZ6AyoC81DubHUxZusGvPsxcpzCA4J-F20uaia8cpYqzKJdCsNonCH_W8cbns1CINRm6oiu1Fifpk16t41K/s1600/352_Edge_Of_Array_164268-c_branded.png" height="252" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span class="Apple-style-span" style="font-size: small;">Fig. 7 Edge of V-NAND flash array</span></td></tr>
</tbody></table>
<br />
On the left side of the image we can see the array proper. SEM images can always be confusing, but it appears that the polySi bitline cylinders are staggered, and the slots between wordlines are filled with tungsten to contact the substrate for the lower select transistors. Fig. 8 shows things in a little more detail, and we can clearly see that the bitline contacts are staggered. We can also see that there are 36 layers in the stack; 32 wordlines, plus two dummy wordlines, plus the select transistors at top and bottom.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhJliauTwsi3lItAuM3GUWXM4cesD1RRi6nryjqTCqMnfHWNuHX4UrIQNOYHICYuGx16qKCPbsm4_8W3mmsDIbCgjm_tOEnbky6fmVf9AXbCVP39aJmCVpjqE2NEqnLtGzC3UARUad46P0L/s1600/356_FlashArray_24K_164268-c_branded.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhJliauTwsi3lItAuM3GUWXM4cesD1RRi6nryjqTCqMnfHWNuHX4UrIQNOYHICYuGx16qKCPbsm4_8W3mmsDIbCgjm_tOEnbky6fmVf9AXbCVP39aJmCVpjqE2NEqnLtGzC3UARUad46P0L/s1600/356_FlashArray_24K_164268-c_branded.png" height="296" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span class="Apple-style-span" style="font-size: small;">Fig. 8 Close-up image of V-NAND flash array</span></td></tr>
</tbody></table>
<br />
At the moment that's as far as we've got; we don't yet have any materials analysis, but my guess is that the three interconnect layers are tungsten, copper and aluminum, as in a lot of other Samsung memory chips.<br />
<br />
We will of course being preparing a report on this seminal part, so for more details contact <a href="mailto:info@chipworks.com" target="_blank">Chipworks</a>, or keep an eye on my Twitter account, @ChipworksDick. Once the dust has settled, I hope to get into a bit more detail in a future blog in a few months time.<br />
<br />
[1] J. Jang et al., "<i>Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory</i>", Dig. Symp. VLSI Tech., pp. 192-193, June 2009<br />
<br />
[2] K-T Park et al., "<i>Three-Dimensional 128Gb MLC Vertical NAND Flash-Memory with 24-WL Stacked Layers and 50MB/sHigh-Speed Programming</i>", Proc. ISSCC, pp. 334-335, Feb. 2014<br />
<br />Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-5918743804686354152014-07-18T16:08:00.000-04:002014-07-18T16:08:15.299-04:00TSMC 20-nm Arrives – The First Shoe DropsFor us at Chipworks interested in leading edge processes, 2014 so far
has been the year of waiting for parts and processes that have been
announced, but not shown up in the world of commercial production. It
will surprise no-one in the business that they are Intel’s 14-nm, the
20-nm products from any of the big three foundries (in particular TSMC),
and vertical NAND (in particular Samsung, since they are the first
claiming shipment).<br />
<br />
There are of course other products that we are
anticipating such as the latest SDRAM, STT or resistive RAM, and
anything with TSVs, but they are lower-key and will not get the same
attention from the majority of our customers.<br />
<br />
So now the first
shoe has dropped (must check where that metaphor came from!), and we
have a TSMC-fabbed 20-nm part in-house. It is in the lab at the moment,
and we are waiting for the analysis results.<br />
<br />
It will be
interesting to see what changes TSMC has made from the 28-nm process; in
general, I expect mostly a shrink of the latter process, with no change
to the materials of the high-k stack, though maybe to the sequence. At
28-nm the high- k was put down first, before the dummy poly gate, and it
makes sense to move that deposition to after poly gate removal. That
way, the high-k layer does not have to suffer the poly formation and
source-drain engineering process steps, saving it from quite a bit of
thermal processing.<br />
<br />
Below is an illustration of a NMOS transistor
from a Qualcomm Snapdragon 800, fabricated in the TSMC 28HPM process.
The slight indent at the bottom of the metal stack (indicated by the
arrow), above the high-k layers, indicates that the high-k was formed
before the polysilicon deposition and the subsequent source/drain
engineering.<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhGceURJ2yBHyCUjO-bLsDVVw_AJhtJ5XyzYGCM8BQerBXbynt0GCommmfJS0S81CNIBgDbdlwl6dIRw-A-k7iR50rzC07p06lCBPMByMBeowEEVtCCRDOJcsDvYBu6udQrEz4pm3R2UAE2/s1600/TSMC+28+NMOS.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhGceURJ2yBHyCUjO-bLsDVVw_AJhtJ5XyzYGCM8BQerBXbynt0GCommmfJS0S81CNIBgDbdlwl6dIRw-A-k7iR50rzC07p06lCBPMByMBeowEEVtCCRDOJcsDvYBu6udQrEz4pm3R2UAE2/s1600/TSMC+28+NMOS.png" height="166" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Fig. 1 NMOS Transistor in Qualcomm Snapdragon 800</td></tr>
</tbody></table>
The dark line at the perimeter of the metal gate is the tantalum-based
barrier layer between the Ti-Al work-function doping layer and the TiAlN
work-function layer, and is the first layer formed after the dummy poly
removal. Intel used this sequence for their 45-nm process, but modified
it at the 32-nm node to deposit the high-k stack after poly removal
(high-k last – see below).<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhQE7hTREwCa8XbXHYS2B4fPya04oJyYWH_JHHOYGxfUlFu9Sk1wkdLdQ3BEsiOomaP_eYFYTLV3XCd0bhpVtHPPJvUdlZeitsHcXz4hN2sY-N1ZLIPCJN-we6cmrLB3QP3GVw6N93VJGpC/s1600/Intel+32nm+NMOS.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhQE7hTREwCa8XbXHYS2B4fPya04oJyYWH_JHHOYGxfUlFu9Sk1wkdLdQ3BEsiOomaP_eYFYTLV3XCd0bhpVtHPPJvUdlZeitsHcXz4hN2sY-N1ZLIPCJN-we6cmrLB3QP3GVw6N93VJGpC/s1600/Intel+32nm+NMOS.png" height="320" width="310" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Fig. 2 Intel 32-nm NMOS Transistor</td></tr>
</tbody></table>
You can
see that Intel also adopted raised source/drains, with stacking faults
to apply tensile stress; we will see if TSMC does the same in their
second generation gate-last HKMG process. They could also change the
gate fill metal, since in a smaller gate it may be difficult to use the
PVD Ti/Al/Cu from the 28-nm sequence.<br />
<div data-mce-style="text-align: left;" style="text-align: left;">
</div>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhl9YFkoL4NATao0MWKXYPJIx9hvtuDJSuDZV1J3Dz94USRufuQe4vzKin785xPrxwq-LPFNFv4k12vxpRiLH8rP3X_Yx3JZF4-t-HdgSLIDTGUZK9Rv4ZPYVIKrXqvy7BPutxU0IWgVxRR/s1600/TSMC+28+PMOS.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhl9YFkoL4NATao0MWKXYPJIx9hvtuDJSuDZV1J3Dz94USRufuQe4vzKin785xPrxwq-LPFNFv4k12vxpRiLH8rP3X_Yx3JZF4-t-HdgSLIDTGUZK9Rv4ZPYVIKrXqvy7BPutxU0IWgVxRR/s1600/TSMC+28+PMOS.png" height="305" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Fig. 3 PMOS Transistor in Qualcomm Snapdragon 800</td></tr>
</tbody></table>
<div data-mce-style="text-align: left;" style="text-align: left;">
When
it comes to PMOS, I also expect a high-k last version of the 28-nm gate
structure, with the latest version of e-SiGe source/drains, likely with
a sigma-cavity etch to the (111) planes. We already have raised
source/drains, and the Ge content is ~50%, so not much opportunity for
change there.</div>
<div data-mce-style="text-align: left;" style="text-align: left;">
</div>
As for the back-end, presumably there will be a reduction in the
k-value of the low-k dielectric, and maybe some thinning of the barrier
layer in the metal trenches, both of which are trends that progress
relatively slowly by comparison with the front-end.<br />
<br />
Back in May, Applied Materials <a data-mce-href="http://www.appliedmaterials.com/company/news/press-releases/2014/05/applied-materials-introduces-the-biggest-materials-change-to-interconnect-technology-in-15-years" href="http://www.appliedmaterials.com/company/news/press-releases/2014/05/applied-materials-introduces-the-biggest-materials-change-to-interconnect-technology-in-15-years" target="_blank">announced</a>
a cobalt CVD system aimed at improving copper fill and
electro-migration performance. I wouldn’t have expected to see this in
use yet, but at Semicon I heard that over 90 of these systems have
already been shipped, so there is at least a possibility that we’ll see
cobalt in our 20-nm metallization.<br />
<br />
All pure speculation, but as a blogger and analyst, I’m paid to speculate!<br />
<br />
As for "the first shoe drop", it's a variant on "<a data-mce-href="http://voices.yahoo.com/origin-meaning-waiting-other-shoe-to-514573.html" href="http://voices.yahoo.com/origin-meaning-waiting-other-shoe-to-514573.html" target="_blank">waiting for the other shoe to drop</a>";
apparently it's a reference to cheap apartment housing where tenants
would hear their neighbours above taking off and dropping their first
shoes on to the floor; and then wait for the second shoes to drop.Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-2738083920395526592014-02-07T15:29:00.000-05:002014-02-07T15:46:05.731-05:00Intel’s e-DRAM Shows up in the Wild<div class="separator" style="clear: both; text-align: center;">
</div>
When Intel launched their Haswell series chips last June, they stated that the high-end systems would have embedded DRAM, as a separate chip in the package; and they gave a paper at the <a href="http://www.vlsisymposium.org/" target="_blank">VLSI Technology Symposium</a> [1] that month, and another at <a href="http://www.his.com/~iedm/" target="_blank">IEDM</a> [2].<br />
<br />
It took us a while to track down a couple of laptops with the requisite Haswell version, but we did and now we have a few images that show it’s a very different structure from the other e-DRAMs that we’ve seen.<br />
<br />
IBM has been using e-DRAM for years, and in all of their products since the 45-nm node. They have progressed their trench DRAM technology to the 22-nm node [3], though we have yet to see that in production.<br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjPi5iGFxkX-iyyBUWpDMAkZhZkmzdLh1bVnIt08mcU1CIKy5iHJtDNEAngKLLZzjU2r6F-lbCeRMzgLhWMCjU7ERJpn6l-Y7l0VosNzoHIUp9SeJXKhh2Y3XsvTIcLQQsXxECkh5LiFcNE/s1600/IBM+45nm_branded.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjPi5iGFxkX-iyyBUWpDMAkZhZkmzdLh1bVnIt08mcU1CIKy5iHJtDNEAngKLLZzjU2r6F-lbCeRMzgLhWMCjU7ERJpn6l-Y7l0VosNzoHIUp9SeJXKhh2Y3XsvTIcLQQsXxECkh5LiFcNE/s1600/IBM+45nm_branded.png" height="276" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Embedded DRAM in IBM Power 7+ (32-nm)</td></tr>
</tbody></table>
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TSMC and Renesas have also used e-DRAM in the chips they make for the gaming systems, the Microsoft Xbox and the Nintendo Wii. They use a more conventional form of memory stack with polysilicon wine-glass-shaped capacitors. TSMC uses a cell-under-bit stack where the bitline is above the capacitors, and Renesas a cell-over-bit (COB) structure with the bitline below.<br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgOUSqV2PEGl2yFMTYzj8mLSLih1T9LOvNJY7xzt-bVyNnNClk58C8tYSU4EJmPeUVuf2kMxv2Dc4s2tLm_jc62B4dw_wh35Iq9Gq18cwz6XpisJHE270LYoX7YIQf80dWttT_FHcP9DD4e/s1600/TSMC+65nm_branded-ann.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgOUSqV2PEGl2yFMTYzj8mLSLih1T9LOvNJY7xzt-bVyNnNClk58C8tYSU4EJmPeUVuf2kMxv2Dc4s2tLm_jc62B4dw_wh35Iq9Gq18cwz6XpisJHE270LYoX7YIQf80dWttT_FHcP9DD4e/s1600/TSMC+65nm_branded-ann.png" height="377" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Embedded DRAM in Microsoft Xbox GPU fabbed by TSMC (65-nm) </td></tr>
</tbody></table>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh-XYAPsS-URZ8nMrW3Q_6gVLvO5cE4unbUdyU089pubiCkilmkPWtK42ZPwHDX2gaSgOoKvZImvD85IbDmvxggpZK4PO363j75eV-Q1Hx2ADvRDM9yBTemmP1yTrXhfAbik6qayPt8uxU0/s1600/Renesas+45nm_branded.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh-XYAPsS-URZ8nMrW3Q_6gVLvO5cE4unbUdyU089pubiCkilmkPWtK42ZPwHDX2gaSgOoKvZImvD85IbDmvxggpZK4PO363j75eV-Q1Hx2ADvRDM9yBTemmP1yTrXhfAbik6qayPt8uxU0/s1600/Renesas+45nm_branded.png" height="326" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Embedded DRAM in Nintendo Wii U GPU fabbed by Renesas (45-nm)</td><td class="tr-caption" style="text-align: center;"></td><td class="tr-caption" style="text-align: center;"></td><td class="tr-caption" style="text-align: center;"></td></tr>
</tbody></table>
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Intel also uses a COB stack, but they build a MIM capacitor in the
metal-dielectric stack using a cavity formed in the lower metal level
dielectrics. The part is fabbed in Intel’s 9-metal, 22-nm process:<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhSK5ANdVo6JLWLlXrqna0IZlCeDA8olfniHksIzJmUUqoNXFwZvhryhryOidVVp5ZbpeiwY8Kltyi8P_pnJEjNlV43UwfDysFIUEydllQg0plS3ics1BwZCZPSDzO_i6WTWCc-ZmOiR-Ug/s1600/352_general_structure-c_branded.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhSK5ANdVo6JLWLlXrqna0IZlCeDA8olfniHksIzJmUUqoNXFwZvhryhryOidVVp5ZbpeiwY8Kltyi8P_pnJEjNlV43UwfDysFIUEydllQg0plS3ics1BwZCZPSDzO_i6WTWCc-ZmOiR-Ug/s1600/352_general_structure-c_branded.png" height="287" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"> <span id="goog_1369744304"></span><span id="goog_1369744305"></span>G<span id="goog_1369744313"></span><span id="goog_1369744314"></span>eneral structure of Intel’s 22-nm embedded DRAM part from Haswell package</td></tr>
</tbody></table>
When we zoom in and look at the edge of the capacitor array, we can see that the M2 – M4 stack has been used to form the mould for the capacitors.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgRMQXNQtbVeAKvNWlNClzGkKzruBIiRscs9zbWhXFS-uP6PL4PY_f71YjMjW66hgXk2kdZw8DeICZk5-JPrsXlNU7SNaUk7q4AGixYckrHy4MKgmp97DAykqbr1u3fTRI9TQMzoui-fHLm/s1600/416_array_end-c_branded-ann.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgRMQXNQtbVeAKvNWlNClzGkKzruBIiRscs9zbWhXFS-uP6PL4PY_f71YjMjW66hgXk2kdZw8DeICZk5-JPrsXlNU7SNaUk7q4AGixYckrHy4MKgmp97DAykqbr1u3fTRI9TQMzoui-fHLm/s1600/416_array_end-c_branded-ann.png" height="330" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Intel’s 22-nm embedded DRAM stack</td></tr>
</tbody></table>
Looking a little closer, we can see the wordline transistors on the tri-gate fin, with passing wordlines at the end of each fin. Two capacitors contact each fin, and the bitline contact is in the centre of the fin.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhTsXBseziQPCtSLd1zPSf5BXH9MSHN4cDbwyLJLCo_al60wT-JypEQzWMWF102WReDunwOHb8-Pdm22yPwz3koe4V8Z2At9BAVMZOd78PGkNgOasFp43qIRv2OvGYDA6N3x4IpI0dfYPuc/s1600/353_structure-c_branded-c-ann.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhTsXBseziQPCtSLd1zPSf5BXH9MSHN4cDbwyLJLCo_al60wT-JypEQzWMWF102WReDunwOHb8-Pdm22yPwz3koe4V8Z2At9BAVMZOd78PGkNgOasFp43qIRv2OvGYDA6N3x4IpI0dfYPuc/s1600/353_structure-c_branded-c-ann.png" height="310" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">A closer look at the Intel 22-nm embedded DRAM stack</td></tr>
</tbody></table>
We can see some structure in the capacitors, but at the moment we have not done any materials analysis. A beveled sample lets us view the plan-view:<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg5G_rCOo5c8ytng0BRtD2B1c8CtfXg_Cz0998jV4Y1nTW6_igauTfA1cwOcSwiOjeY_Ld99LcGmTwNaqqvsIITYOZnPErcxn6CvaJp-vmXQ-gATJHUCTIAMRK9sDMM7kj3pEZ1G401k2-d/s1600/343_M2_80K-c_branded-ann.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg5G_rCOo5c8ytng0BRtD2B1c8CtfXg_Cz0998jV4Y1nTW6_igauTfA1cwOcSwiOjeY_Ld99LcGmTwNaqqvsIITYOZnPErcxn6CvaJp-vmXQ-gATJHUCTIAMRK9sDMM7kj3pEZ1G401k2-d/s1600/343_M2_80K-c_branded-ann.png" height="212" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Plan-view image of the Intel 22-nm embedded DRAM capacitors</td></tr>
</tbody></table>
The capacitors are clearly rectangular, but again in the SEM we cannot see any detailed structure. We’ll have to wait for further analysis with the TEM for that!<br />
<br />
Intel claims a cell capacitance of more than 13 fF and a cell size of 0.029 sq. microns, so about a third of their 22-nm SRAM cell area of ~0.09 sq. microns, and a little larger than the IBM equivalent of 0.026 sq. microns. The wordline transistors are low-leakage trigate transistors with an enlarged contacted gate pitch of 108 nm (the minimum CGP is 90 nm).<br />
<br />
In the Haswell usage the die is used as a 128 MB L4 cache, with a die size of ~79 sq. mm, co-packaged with the CPU.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgvoW91Z7FRwjKfHoFGacmBPuY8hE0tU6XGmtlqtSB_Bk-HRsgs9LQAXo2-g786jcjZcRF1PEWfLCSDaVkhE7mMrL-mlmTd-CsNOrraw9K14ixi0yA8E812mZgOni19owQTOl5w8eZJoCyA/s1600/Haswell+pkg.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgvoW91Z7FRwjKfHoFGacmBPuY8hE0tU6XGmtlqtSB_Bk-HRsgs9LQAXo2-g786jcjZcRF1PEWfLCSDaVkhE7mMrL-mlmTd-CsNOrraw9K14ixi0yA8E812mZgOni19owQTOl5w8eZJoCyA/s1600/Haswell+pkg.png" height="320" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Intel Haswell CPU with co-packaged eDRAM</td></tr>
</tbody></table>
Intel got out of the commodity DRAM business almost thirty years ago; it will be interesting to see where they take their new entry, though not likely into competition with the big three suppliers. Their “Knights Landing” high-performance computing (HPC) platform is <a href="http://www.realworldtech.com/knights-landing-details/" target="_blank">reported</a> to use 16 GB of eDRAM, which will take the equivalent of 128 of these chips, so perhaps the future is in HPC and gaming systems such as the one we bought to get the part.<br />
<br />
<b>References</b><br />
<br />
[1] R. Brain et al., <i>A 22nm High Performance Embedded DRAM SoC Technology Featuring Tri-gate Transistors and MIMCAP COB</i>, Proc VLSI Symp 2013, pp. 16-17.<br />
<br />
[2] Y. Wang et al., <i>Retention Time Optimization for eDRAM in 22nm Tri-Gate CMOS Technology</i>, Proc IEDM 2013, pp. 240-243.<br />
<br />
[3] S. Narasimha et al., <i>22nm High-Performance SOI Technology Featuring Dual-Embedded Stressors, Epi-Plate High-K Deep-Trench Embedded DRAM and Self-Aligned Via 15LM BEOL</i>, Proc. IEDM 2012 pp. 52-55.<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
</div>
<span id="goog_1369744291"></span>Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com1tag:blogger.com,1999:blog-5488132572864585098.post-11633570466649874182013-12-06T09:54:00.000-05:002013-12-06T10:31:01.848-05:00IEDM 2013 Preview<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">Next week the researchers
and practitioners of the electron device world will be gathering in Washington
D.C. for the </span><span style="mso-ansi-language: EN-US;">2013 <a href="http://www.his.com/~iedm"><span style="color: blue;">IEEE International Electron Devices Meeting</span></a>.<span style="mso-spacerun: yes;"> </span>To quote the conference web front page, “</span><span lang="EN-GB">IEDM is the flagship conference for nanometer-scale CMOS transistor
technology, advanced memory, displays, sensors, MEMS devices, novel quantum and
nano-scale devices and phenomenology, optoelectronics, devices for power and
energy harvesting, high-speed devices, as well as process technology and device
modeling and simulation. The conference scope not only encompasses devices in
silicon, compound and organic semiconductors, but also in emerging material
systems.”<span style="mso-spacerun: yes;"> </span><o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">From my
perspective at <a href="http://www.chipworks.com/"><span style="color: blue;">Chipworks</span></a>, focused on
chips that have made it to production, it’s the conference where companies
strut their technology, and post some of the research that may make it into
real product in the next few years.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">In the last few
days I’ve gone through the <a href="http://www.his.com/~iedm/program/13advprg.pdf"><span style="color: blue;">advance program</span></a>, and
here’s my pick of what I want to try and get to, in more or less chronological
order.<span style="mso-spacerun: yes;"> </span>As usual there are overlapping
sessions with interesting papers in parallel slots, but we’ll take the decision
as to which to attend on the conference floor.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">For the second year
the conference starts on the Saturday afternoon, with a set of six 90-minute
tutorials on a range of leading-edge topics:<o:p></o:p></span></div>
<br />
<ul style="margin-top: 0in;" type="disc">
<li class="MsoNormal" style="margin: 6pt 0in 0pt; mso-list: l1 level1 lfo1;"><i style="mso-bidi-font-style: normal;"><span style="mso-ansi-language: EN-US;">Nano
Electronics – The use of Low-Dimensional Systems for Device Applications, </span></i><span style="mso-ansi-language: EN-US;">Joerg Appenzeller, Purdue University <o:p></o:p></span></li>
<li class="MsoNormal" style="margin: 6pt 0in 0pt; mso-list: l1 level1 lfo1;"><i style="mso-bidi-font-style: normal;"><span style="mso-ansi-language: EN-US;">Interface
Properties for SiC and GaN MOS Devices, </span></i><span style="mso-ansi-language: EN-US;">T. Paul Chow, Rensselaer Polytechnic Institute<o:p></o:p></span></li>
<li class="MsoNormal" style="margin: 6pt 0in 0pt; mso-list: l1 level1 lfo1;"><i style="mso-bidi-font-style: normal;"><span style="mso-ansi-language: EN-US;">Energy
Harvesting for Self-Powered Electronic Systems, </span></i><span style="mso-ansi-language: EN-US;">Rob van Schaijk, R&D Manager Sensors
and Energy Harvesters, Holst Centre / IMEC<o:p></o:p></span></li>
<li class="MsoNormal" style="margin: 6pt 0in 0pt; mso-list: l1 level1 lfo1;"><i style="mso-bidi-font-style: normal;"><span style="mso-ansi-language: EN-US;">Tunnel
FETs - Beating the 60 mV/Decade Limit, </span></i><span style="mso-ansi-language: EN-US;">Erik Lind, EIT, Lund University<o:p></o:p></span></li>
<li class="MsoNormal" style="margin: 6pt 0in 0pt; mso-list: l1 level1 lfo1;"><i style="mso-bidi-font-style: normal;"><span style="mso-ansi-language: EN-US;">Atomic-Scale
Modeling and Simulations for Nanoelectronics, </span></i><span style="mso-ansi-language: EN-US;">Sumeet C. Pandey and Roy Meade,Emerging
Memory Group, Process R&D, Micron Technology Inc.<o:p></o:p></span></li>
<li class="MsoNormal" style="margin: 6pt 0in 0pt; mso-list: l1 level1 lfo1;"><i style="mso-bidi-font-style: normal;"><span style="mso-ansi-language: EN-US;">3D
Chip Stacking, </span></i><span style="mso-ansi-language: EN-US;">Mukta
Farooq, Systems & Technology Group, IBM<o:p></o:p></span></li>
</ul>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">The first three
are from 2.45 – 4.15, and the remainder from 4.30 – 6.00.<span style="mso-spacerun: yes;"> </span>I won’t make it to any of them; dedicated
nerd I may be, but I want at least some of my weekend!<o:p></o:p></span></div>
<br />
<div style="margin-top: 6pt;">
<span lang="EN-GB">On Sunday December 4<sup>th</sup>,
we start with the <a href="http://www.his.com/~iedm/program/courses.html"><span style="color: blue;">short
courses</span></a>, “<b style="mso-bidi-font-weight: normal;">Challenges of 10nm and 7nm
CMOS Technologies</b>” and “</span><b><span style="mso-ansi-language: EN-US;">Beyond
CMOS: Emerging Materials and Devices</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">”.<span style="mso-spacerun: yes;"> </span><o:p></o:p></span></div>
<br />
<div style="margin-top: 6pt;">
<span style="font-family: "TimesNewRomanPSMT","serif"; font-size: 11pt; mso-ansi-language: EN-US; mso-bidi-font-family: TimesNewRomanPSMT;">Aaron Thean of
IMEC </span><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">has
organised the former, and we have some impressive speakers – </span><span style="font-family: "TimesNewRomanPSMT","serif"; font-size: 11pt; mso-ansi-language: EN-US; mso-bidi-font-family: TimesNewRomanPSMT;">Frederic Boeuf, ST Microelectronics</span><span lang="EN-GB" style="mso-bidi-font-weight: bold;">, (</span><b><span style="mso-ansi-language: EN-US;">Device Challenges and Opportunities for 10nm
and Below CMOS Nodes</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">), Zsolt Tokei, also of IMEC, (<b>Challenges of 10nm & 7nm Advanced
Interconnect</b>), </span><span style="font-family: "TimesNewRomanPSMT","serif"; font-size: 11pt; mso-ansi-language: EN-US; mso-bidi-font-family: TimesNewRomanPSMT;">Andy Wei,
GLOBALFOUNDRIES</span><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">, (<b>Process Integration Challenges in 10nm CMOS Technology</b>), </span><span style="mso-ansi-language: EN-US;">Paul Franzon, NCSU</span><span lang="EN-GB">, (</span><b><span style="mso-ansi-language: EN-US;">Manufacturing, Design, and Test of 2.5D- and
3D-Stacked ICs</span></b><span lang="EN-GB" style="mso-bidi-font-weight: bold;">)</span><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">, and </span><span style="font-family: "TimesNewRomanPSMT","serif"; font-size: 11pt; mso-ansi-language: EN-US; mso-bidi-font-family: TimesNewRomanPSMT;">Mark Neisser, Sematech</span><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> (<b>Lithography
Challenges and EUV Readiness for 10nm and Beyond</b>). With 14-nm product
expected to hit the market next year, we need to look ahead, so this is
appropriate<span style="mso-spacerun: yes;"> </span>- on the Intel clock, 10-nm
is only two - three years away!<span style="mso-spacerun: yes;"> </span><o:p></o:p></span></div>
<br />
<div style="margin-top: 6pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">I’m now telling folks to think about the end of silicon, at least as we
know it, since my brain will not wrap around the idea of 10- and 7-nm gates,
and 10-nm gates are only 30 – 40 atoms across, depending on orientation!
There’s lots of talk about integrating high-mobility materials onto silicon
(imec had an <a href="http://www.imec-nl.nl/nl_en/press/imec-news/imeciiivfinfet.html"><span style="color: blue;">announcement
about InGaAs finFETs</span></a> only a few weeks ago), so this course will help
put that into context and cover off how the transistors fit into the rest of
the stack.<b><o:p></o:p></b></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Tom Theis of SRC has set up the other short
course; now that we are reaching the end of silicon transistors, where do we go
beyond CMOS? <o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Ken Uchida of Keio University reprises some of
the first course with a session on <b>Extending the FET</b>; then Adrian M.
Ionescu from the Ecole Polytechnique Federale de Lausanne discusses <b>Tunnel
FETs</b> to give insights into perhaps the best known low-voltage device.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b><span style="mso-ansi-language: EN-US;">Nanomagnetic Devices </span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">are reviewed by Rolf Allenspach from IBM Zurich
Research Labs, looking at the material properties and challenges, and some example
devices.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">All of these futuristic devices have to be
compared to each other to see which ones have practical potential, so Dmitri
Nikonov of Intel covers off <b>Performance Benchmarking Methodology for
Emerging Devices</b>, looking at the rigorous methodology developed by the SRC’s
Nanoelectronics Research Initiative, with some comparative results.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">The final talk is on <b>Emerging Devices for
Quantum Computing </b>by Michelle Simmons from the University of New South
Wales, showing the device requirements for a practical quantum computer, then a
quick survey of exploratory devices, and a closer look at one or two promising
device concepts.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">So some good solid stuff – although the
courses make a long Sunday, from 9 a.m. to 5.30 p.m., but it’s worth sticking
around to the end.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">For the first time I can remember the Sunday evening
has some extra sessions; Sematech is hosting a session on “<b><a href="http://www.cvent.com/events/beyond-cmos/event-summary-268419d56bcd4983bd29ee8862c06abb.aspx"><span style="color: blue;">Beyond
CMOS</span></a></b>” at the Fairfax at Embassy Row, from 5.30 – 8.35; and Leti will
host a workshop on “</span><b><span lang="EN-GB"><a href="http://leti2013-iedm.insight-outside.fr/"><span style="color: blue;">Latest Advances in
Cost-effective and Power-efficient Technologies for the Future of the
Semiconductor Industry</span></a></span></b><span lang="EN-GB" style="mso-bidi-font-weight: bold;">” from 6 – 9 pm at the Churchill Hotel, across the street from the
Hilton.</span><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"><o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt; tab-stops: list .5in;">
<span lang="EN-GB">Monday morning we have the <b style="mso-bidi-font-weight: normal;">plenary
session</b>, with three pertinent talks on the challenges of contemporary
electronics: <o:p></o:p></span></div>
<br />
<ul style="margin-top: 0in;" type="disc">
<li class="MsoNormal" style="margin: 6pt 0in 0pt; mso-list: l0 level1 lfo3;"><b><i style="mso-bidi-font-style: normal;"><span style="mso-ansi-language: EN-US;">Graphene
Future Emerging Technology, </span></i></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">by </span><span style="mso-ansi-language: EN-US;">Andrea Ferrari, from the University of Cambridge – given the developments
in this field in the last few years, it’s time to look ahead and try and
create a roadmap for this potentially disruptive technology, so this
should be illuminating;</span></li>
<li class="MsoNormal" style="margin: 0in 0in 0pt; mso-list: l2 level1 lfo2; tab-stops: list .5in;"><b><i style="mso-bidi-font-style: normal;"><span style="mso-ansi-language: EN-US;">Heterogeneous
3D Integration – Technology Enabler Toward Future Super-Chips, </span></i></b><span style="mso-ansi-language: EN-US;">Mitsumasa Koyanagi, Tohoku University – we
are already seeing a form of heterogeneous integration in RF front-end
modules (but at the package level), and with <a href="https://chipworks.secure.force.com/catalog/ProductDetails?sku=LUL-1000001&viewState=DetailView&cartID=&g=&parentCategory=&navigationStr=CatalogSearchInc&searchText=luxtera"><span style="color: blue;">Luxtera</span></a>’s
<a href="http://www.luxtera.com/"><span style="color: blue;">optical interface chips</span></a>, but this
talk will describe the higher levels of integration being researched at
Tohoku U and elsewhere.<o:p></o:p></span></li>
<li class="MsoNormal" style="margin: 0in 0in 0pt; mso-list: l2 level1 lfo2; tab-stops: list .5in;"><b><i style="mso-bidi-font-style: normal;"><span style="mso-ansi-language: EN-US;">Smart
Mobile SoC Driving the Semiconductor Industry: Technology Trend,
Challenges and Opportunities</span></i></b><b><span style="mso-ansi-language: EN-US;">, </span></b><span style="mso-ansi-language: EN-US;">Geoffrey Yeap,
Qualcomm. As VP of Technology, Geoffrey Yeap has been at the heart of the
mobile revolution, and helped push the company into the top ten; so this
should be an interesting review of the last few years of mobile chip
developments, and the challenges of squeezing more and more functionality
onto ICs, for more and more RF bands, and in ever thinner phones.<o:p></o:p></span></li>
</ul>
<span lang="EN-GB">At lunchtime ASM is hosting their regular
IEDM seminar (Monday this year, instead of the Wednesday as in previous years)
on <b style="mso-bidi-font-weight: normal;"><a href="http://www.asm.com/en/Pages/IEDM-Reminder.aspx"><span style="color: blue;">Integrating High Mobility
Materials</span></a>, </b>again at the Churchill Hotel.<o:p></o:p></span><br />
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">After lunch we
have seven parallel sessions coming up! <b style="mso-bidi-font-weight: normal;">Session
2</b> gets straight into the way-ahead material with papers on germanium &
III-V CMOS devices, although we seem to be moving away from R towards D in the
R&D spectrum; for example, paper <b style="mso-bidi-font-weight: normal;">2.8</b>
from IBM builds InGaAs n- and SiGe p-MOSFETs on hybrid substrates formed by
direct wafer bonding of SiGe and InGaAs layers. <o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b style="mso-bidi-font-weight: normal;"><span lang="EN-GB">Session 3</span></b><span lang="EN-GB"> details MRAM and
NAND flash memories, starting with an invited talk by AIST on </span><b><span style="mso-ansi-language: EN-US;">Future Prospects of MRAM Technologies (3.1)</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">, and the session
ends<b> </b></span><span lang="EN-GB">with papers from Hynix and Macronix, the
former on a 1x-nm multi-level cell NAND flash <b style="mso-bidi-font-weight: normal;">(3.6)</b>, and the latter on a dual-channel 3D NAND flash <b style="mso-bidi-font-weight: normal;">(3.7)</b>.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">In <b style="mso-bidi-font-weight: normal;">session 4</b>, we have the more futuristic
topic of <b style="mso-bidi-font-weight: normal;">Steep Slope Devices</b>,
including papers from imec <b style="mso-bidi-font-weight: normal;">(4.2)</b> and
Intel<b style="mso-bidi-font-weight: normal;"> (4.3)</b> on tunnel FETs.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">Now that we are
into the finFET era, there is an interesting simulation paper in <b style="mso-bidi-font-weight: normal;">session 5</b>; </span><b><span style="mso-ansi-language: EN-US;">Analysis of Dopant Diffusion and Defects in Fin
Structure (5.7)</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">, a joint paper by Panasonic and imec.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b style="mso-bidi-font-weight: normal;"><span lang="EN-GB">Session 6</span></b><span lang="EN-GB"> focuses on </span><b><span style="mso-ansi-language: EN-US;">Power Devices</span></b><span lang="EN-GB">, with
an indication that TSMC is getting into the business; they have a joint paper
with Honk Kong UST on interface traps in Al<sub>2</sub>O<sub>3</sub>/AlGaN/GaN
MIS devices <b style="mso-bidi-font-weight: normal;">(6.3)</b>. Mitsubishi is
giving an invited talk on high voltage and large current SiC power devices <b style="mso-bidi-font-weight: normal;">(6.5)</b>, and we get back to MOS with a
joint paper on the operating limits of LDMOS from NXP and U Twente.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">The first two
papers in <b style="mso-bidi-font-weight: normal;">session 7</b> discuss the
reliability degradation caused by TSVs and 3D stacking, as measured by DRAM
retention time; it appears that if wafers are thinned to 30 microns or less the
DRAM performance drops off significantly due to stresses caused by the TSVs and
microbumps <b style="mso-bidi-font-weight: normal;">(7.1, 7.2)</b>.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">This year’s IEDM
has focus sessions, and <b style="mso-bidi-font-weight: normal;">session 8</b> is
the first, on </span><b><span style="mso-ansi-language: EN-US;">Sensors and Microsystems
for Biomedical Applications</span></b><span lang="EN-GB">, with seven invited
talks on different aspects of biosensors and biomedical devices.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">Then in the
evening we have the conference reception at 6.30, through until 8 pm.<o:p></o:p></span></div>
<br />
<span lang="EN-GB">Tuesday morning we
have another seven parallel sessions, starting with <b style="mso-bidi-font-weight: normal;"><span style="color: black;">session 9</span></b> on </span><b><span style="mso-ansi-language: EN-US;">Advanced CMOS Technology, </span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">so one I will
definitely be targeting. The first paper <b>(9.1)</b> is TSMC’s launch of their
16-nm finFET</span><o:wrapblock><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"><v:stroke joinstyle="miter"><v:formulas> process, with a claimed doubling of logic density over their 28-nm process, with more than 35% speed gain or over 55% power reduction, and a 0.07 sq. micron 6T SRAM cell size.<o:p></o:p> <v:f eqn="if lineDrawn pixelLineWidth 0"> <v:f eqn="sum @0 1 0"> </v:f></v:f></v:formulas></v:stroke></v:shapetype></o:wrapblock><br />
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</v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas>
<v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f">
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<v:imagedata o:title="Wu (9" src="file:///C:\Users\DICKJA~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.jpg">
<w:wrap anchory="margin" type="topAndBottom">
</w:wrap></v:imagedata></v:shape></o:wrapblock><br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjEIK7_Jlr7Uj4rg38Zz3KBtgIH4iIPHYWXbVXNL-wwicFhLKhwdm3WPGv31d4KuNzelJuGmyjblV7QFWj_beP3rrWaCT_gmvmKlhPek747cESo-ivqqQqNsPgfRvvYovkuMB-kYxKBEmGr/s1600/Wu+(9.1)+Fig.2.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjEIK7_Jlr7Uj4rg38Zz3KBtgIH4iIPHYWXbVXNL-wwicFhLKhwdm3WPGv31d4KuNzelJuGmyjblV7QFWj_beP3rrWaCT_gmvmKlhPek747cESo-ivqqQqNsPgfRvvYovkuMB-kYxKBEmGr/s1600/Wu+(9.1)+Fig.2.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Comparison of TSMC 16-nm finFET performance with 28-nm HKMG planar process (Source: TSMC, IEDM)<o:p></o:p></td></tr>
</tbody></table>
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"></span><br />
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">That is followed <b>(9.2)</b> by the competing
20-nm FDSOI process from the ISDA Alliance (IBM, STMicroelectronics, Renesas, GLOBALFOUNDRIES,
SOITEC, and CEA-LETI).<o:p></o:p></span><br />
<o:wrapblock><v:shape id="_x0000_s1027" style="height: 262.35pt; margin-left: 0px; margin-top: 0px; mso-position-horizontal-relative: margin; mso-position-horizontal: center; mso-position-vertical-relative: margin; mso-position-vertical: bottom; mso-wrap-distance-bottom: 7.2pt; mso-wrap-distance-top: 7.2pt; position: absolute; width: 224.6pt; z-index: 251658752;" type="#_x0000_t75">
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</w:wrap></v:imagedata></v:shape></o:wrapblock><br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Paper <b>9.3</b>
takes us into the world of 3D-IC with a</span><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> paper on layered ultrathin-body
(UTB) circuits stacked on 300nm-thick interlayer dielectric (ILD) layers. </span><br />
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"><o:p></o:p></span> </div>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjoPWPPKoWMduPevRJ9wd2nPQdNa2hkU2EvWFQCiDMwYaokjCYUT1JmYzHDEIuwU4yYlPFBGZs-TKqK4wPzAF3ZxUz_7pp511ZPy2hW5S93j8uGXr15CMSVcqtF3hR68gfRxnhzUS3EAbni/s1600/Shen+%25289.3%2529+Fig.3.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="400" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjoPWPPKoWMduPevRJ9wd2nPQdNa2hkU2EvWFQCiDMwYaokjCYUT1JmYzHDEIuwU4yYlPFBGZs-TKqK4wPzAF3ZxUz_7pp511ZPy2hW5S93j8uGXr15CMSVcqtF3hR68gfRxnhzUS3EAbni/s400/Shen+%25289.3%2529+Fig.3.jpg" width="340" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">TEM image of 3D-layered UTB chip (Source: NNDL/Stanford/NTHU/UC Berkely, IEDM)</td></tr>
</tbody></table>
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"></span><br />
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Amorphous silicon layers were deposited and
crystallized with laser pulses, then planarized with low-temperature CMP to
thin the layers, allowing formation of ultrathin, ultraflat devices.<o:p></o:p></span><br />
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">IBM takes the next
slot <b style="mso-bidi-font-weight: normal;">(9.4)</b> with what looks like an
update on their 22-nm gate-first process debuted last year (paper 3.3 last
year), discussing </span><b><span style="mso-ansi-language: EN-US;">2nd
Generation Dual-Channel Optimization with cSiGe for 22nm HP Technology and Beyond</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">.</span><br />
<br />
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Intel also
gives an update, this time on their eDRAM technology disclosed at the VLSI
Symposium in June <b>(Retention Time Optimization for eDRAM in 22nm Tri-Gate
CMOS Technology, 9.5). </b></span><br />
</div>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiP1L_iThNum-AvrHFZpvpQx7arXFUz_fVgNLalO-CIZf2gK04TOgZrlZvjokldp2jxcwFyQsGxLDTdCojxSQu2O87VvpEeVbYLI9sCTO9Cd1iAKsSYsVBxu8aK9afNLcrNz-8COqHoAnSp/s1600/Intel+eDRAM.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="257" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiP1L_iThNum-AvrHFZpvpQx7arXFUz_fVgNLalO-CIZf2gK04TOgZrlZvjokldp2jxcwFyQsGxLDTdCojxSQu2O87VvpEeVbYLI9sCTO9Cd1iAKsSYsVBxu8aK9afNLcrNz-8COqHoAnSp/s400/Intel+eDRAM.png" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Details from Intel eDRAM paper at 2013 VLSI Technology Symposium</td></tr>
</tbody></table>
<span lang="EN-GB"></span><br />
<span lang="EN-GB">The session
finishes up with a paper on embedded flash in a 55-nm process from Fujitsu <b style="mso-bidi-font-weight: normal;">(9.6)</b>, and one on SRAM-like local
interconnect structures for 20-nm middle-of-line metallization from </span><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">GLOBALFOUNDRIES; they
claim that this helps them “achieve industry’s most optimum 20nm technology
offerings”.<o:p></o:p></span><br />
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">So I guess from the above I will be in session
9 all morning, so I will have to give <b>session 10</b> on <b>RRAM and FERAM</b>
a miss, even though there is interesting progress in the field, including 28-nm
RRAM in a paper <b>(10.3)</b> co-authored by TSMC.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b><span style="mso-ansi-language: EN-US;">Session 11 </span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">is focused on <b>Flexible Electronics</b>, a look into the future, but
not too far away, judging by some of the talks. <o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b><span style="mso-ansi-language: EN-US;">Session 12</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is the first on <b>Modeling and Simulation</b>, focusing on <b><span style="color: black;">Technology CAD</span></b><span style="color: black;">, with a
few topics that catch my eye; paper <b>12.2 </b>on <b>Alloy Scattering in SiGe
Channel</b> from Samsung; <b>Mobility in High-K Metal Gate UTBB-FDSOI Devices</b>,
an invited talk <b>(12.5)</b> from STMicroelectronics; <b>Threshold Behavior of
the Drift Region: the Missing Piece in LDMOS Modeling (12.7)</b>, from NXP; and
<b>Copper Through Silicon Via Induced Keep Out Zone for 10nm Node Bulk FinFET
CMOS<span style="mso-spacerun: yes;"> </span>Technology (12.8)</b>, a joint
paper from imec and Synopsys.<o:p></o:p></span></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="color: black; mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">It seems that <b>session 13</b>
is a bit of a catch-all session on <strong>Advanced Manufacturing</strong>, since it includes
invited papers on 3D memory (13.1) from Micron, GaN-on-Si from Toshiba <b>(13.2)</b>,
photonics on SOI by Luxtera and STMicroelectronics <b>(13.3)</b>, TSMC’s take
on glass interposers <b>(13.4)</b> and 450-mm <b>(13.7)</b>, and III-V growth
on 300 mm wafers from Aixtron <b>(13.6)</b>.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="color: black; mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Next we have another
bio-session, <b>BioMEMS and BioSensors</b>, including two DNA analysis-on-chip
papers <b>(14.1 & 14.3).</b> The last parallel session of the morning is <b>session
15</b>, on <b>Reliability of BEOL and FEOL Devices</b>, and it now seems that
graphene and nanotubes have been around long enough that we have an invited
talk on their reliability <b>(15.1)</b>.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span lang="EN-GB">The speaker at the
conference lunch will be</span><span style="mso-ansi-language: EN-US;"> David
Luebke, Senior Director of Research at Nvidia, on the topic, <i>The Current
State-of-the-Art and Advances in Visual/GPU Computing.<o:p></o:p></i></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b style="mso-bidi-font-weight: normal;"><span lang="EN-GB">Session 16</span></b><span lang="EN-GB"> in the
afternoon is about </span><b><span style="mso-ansi-language: EN-US;">III-V Logic</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">, looking ahead to
when silicon can no longer provide the performance needed. <o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b style="mso-bidi-font-weight: normal;"><span lang="EN-GB">Session 17</span></b><span lang="EN-GB"> is another
focus session, this time on </span><b><span style="mso-ansi-language: EN-US;">Analog
and Mixed Signal Circuit/Device Interactions</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">. We have a series of invited talks on the
impact of nanometer scaling and finFETS on analog design and performance, RF
technology, and a look at terahertz RF in CMOS, all of which catch my interest.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">We are back to <b>Sensors, Resonators, and
Microsystems</b> in <b>session 18</b>, and <b>Nanosheet and Nanotube Technology</b>
in <b>session 19</b>, and it seems that molybdenum disulphide is now taking
attention away from graphene since there are a couple of papers on that topic.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b><span style="mso-ansi-language: EN-US;">Session 20</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is another multi-topic group of papers, on <b>Fully Depleted Planar, 3D
Ge Device Technology and RRAM Memory</b> processing. We have TSMC and
GloFo/Samsung/imec talking Ge finFETs <b>(20.1 & 20.4)</b>, Si nanowires
from IBM <strong>(20.2)</strong>, and gate-last FDSOI from STMicroelectronics and CEA-LETI <b>(20.3)</b>;
two papers on doping finFETS by AIST/Nissin and AMAT/GloFo/Hynix <b>(20.5 &
20.6)</b>; and to finish the session two RRAM talks by Macronix/National
TsingHua U and Stanford U <b>(20.7 & 20.8)</b>. The last paper uses block
copolymer self-assembly lithography to get the device down to less than 12 nm.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b><span style="mso-ansi-language: EN-US;">Memory Characterization and Reliability</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> is the subject of <b>Session
21</b>, mostly of resistive memories; <b>Session 22</b> is another <b>Modeling
and Simulation</b> group of papers, this time on <b>Innovative Devices</b>,
mainly resistive memories. <o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">That brings us to the end of the afternoon,
and now we have a dilemma – <i style="mso-bidi-font-style: normal;">three</i> offsite
events – IEDM is getting popular with the industry! <a href="http://www.appliedmaterials.com/"><span style="color: blue;">Applied Materials</span></a> is hosting a
panel on <a href="http://www.appliedmaterials.com/NAND-panel"><span style="color: blue;">"3D NAND Is
a Reality - What's Next?"</span></a> at </span><span class="ccbntxt"><span lang="EN-GB">the Omni Shoreham Hotel from 5 – 7.30 pm; <a href="http://www.coventor.com/"><span style="color: blue;">Coventor</span></a> is also hosting a panel at the
Churchill Hotel, from 5.30 – 8.30, on <a href="http://www.coventor.com/events/join-coventor-and-experts-on-advanced-technology-development/"><span style="color: blue;">“Insights
from the Experts on Advanced Technology Development”</span></a>; and <a href="http://www.synopsys.com/home.aspx"><span style="color: blue;">Synopsys</span></a> is having a <a href="https://events.synopsys.com/sap%28bD1lbiZjPTkxMA==%29/bc/bsp/sap/zeventreg_ext/main.do?view_type=AUTH"><span style="color: blue;">TCAD
reception</span></a>, again at the Churchill, from 6 – 8 pm.<o:p></o:p></span></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span class="ccbntxt"><span lang="EN-GB">Once we’re sated from the hospitality we can wander back to the
Hilton and try and stay awake for the conference evening panels:</span></span><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"><o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b><span style="mso-ansi-language: EN-US;">“Is there life beyond conventional CMOS?”</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> moderated by<span style="mso-bidi-font-style: italic;"> Jeff Welser of IBM – now becoming a perennial
question! The panelists are An Chen (GLOBALFOUNDRIES), Tetsuo Endoh (Tohoku
University), Marc Heyns (IMEC Fellow), Mark Rodwell (UC Santa Barbara), Alan
Seabaugh (Notre Dame), and Ian Young (Intel).<o:p></o:p></span></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-style: italic; mso-bidi-font-weight: bold;">And:<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b><span style="mso-ansi-language: EN-US;">“Will Voltage Scaling in CMOS Technology Come to an END?" </span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">with<b> </b>Kevin
Zhang of Intel as moderator. Panelists for this session are Rob Aitken (ARM), Kelin
Kuhn (Intel), Sreedhar Natarajan (TSMC), Tak Ning (IBM), Ann Steegen (imec),
and Nobuyuki Sugii ( LEAP).<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">Wednesday morning has <b>sessions 25 – 30</b>;
<b>S25</b> on <b>Advanced 3D Packaging and Emerging Memory Systems</b>; TSMC is
detailing an <b>Array Antenna Integrated Fan-out Wafer Level Packaging (25.1), </b>and
Maxim is giving an invited talk on <b>3D Heterogeneous Integration for Analog</b>,
as the first two papers.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b><span style="color: black; mso-ansi-language: EN-US;">S26</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> covers <b>Ge Channel and Nanowire Devices</b>,
obviously looking ahead, but catching my interest are <b>A Group IV Solution
for 7nm FinFET CMOS (26.3)</b>, from Synopsys/Stanford, and <b>A Practical Si
Nanowire Technology… (26.5)</b> from Samsung.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b><span style="mso-ansi-language: EN-US;">Session 27 - Display and Imaging Devices</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> has three papers on thin-film
transistors for displays, and three imaging talks; Sony describes a <b>Three-dimensional
.. 1.20 μm Pixel Back-Illuminated CMOS Image Sensor (27.4)</b>, and Infineon
has a novel <b>Trench Gate Photo Cell</b> <b>(27.6)</b> which could find use as
the ambient light sensor that we see in so many mobile phones.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">We have more III-V and TFET papers in <b>session
28</b>, but including an invited talk from Raydeon (<b>More than Moore: III-V
Devices and Si CMOS Get It Together – 28.5)</b> on integrating III-V devices
with Si CMOS on a common silicon substrate, which should be interesting in
these days of 3D.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b><span style="mso-ansi-language: EN-US;">Session 29</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> has a couple of interesting papers on BEOL from Renesas and Samsung <b>(29.1
& 29.2)</b>, and Hitachi/ASET discusses <b>Fabricating 3D Integrated CMOS
Devices by Using Wafer Stacking and Via-last TSV Technologies (29.5)</b>.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b><span style="mso-ansi-language: EN-US;">Conductive Bridge and Phase Change RAM</span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;"> papers make up <b>session 30</b>; the first
two are CBRAM, and the rest PCM. Micron discusses <b>Interface Engineering for
Thermal Disturb Immune Phase Change Memory Technology</b> in paper <b>30.4</b>.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">After the morning sessions, the <b>IEDM
Entrepreneurs Lunch</b> is back for a second year, with Steve Nasiri, founder
of Invensense, and now angel investor and mentor at Nasiri Ventures LLC, as
guest speaker.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">We are back to <b>Characterization,
Reliability, and Yield </b>in<b> S31 </b>after lunch,<b> </b>with a focus on <b>Device
Variation and Noise</b>. STMicroelectronics is giving an invited presentation
on the <b>Growing Impact of Atmospheric Radiations on sub-65nm CMOS BULK/FDSOI Technologies
(31.1)</b>, we have two papers on SRAM, and the last three discuss random
telegraph noise in MOSFETs, resistive RAM, and HEMTs, respectively.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<b><span style="mso-ansi-language: EN-US;">Session 32 </span></b><span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">is the third <b>Modeling and Simulation session</b>, this time on <b>Modeling
Beyond CMOS Devices, Interconnects and GaN HEMT</b> – getting a bit esoteric
for my focus, unfortunately – but then with all the parallel sessions we have
to miss some of them.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">The last session (numerically), <b>session 33</b>,
covers <b>Circuit/Device Variability and Reliability</b>. Asen Asenov of University
of Glasgow/Gold Standard Simulations has a joint paper with IBM on <b>Simulation
Based Transistor-SRAM Co-Design in the Presence of Statistical Variability and Reliability
(33.1)</b>, detailing the impact of process and statistical variability and
reliability on SRAM cell design in 14nm technology node SOI FinFET
transistors; with Intel’s 14-nm due next year we might get some insights,
though time will tell if they have moved to SOI trigate transistors from the bulk material that they currently use at 22-nm.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="margin: 6pt 0in 0pt;">
<span style="mso-ansi-language: EN-US; mso-bidi-font-weight: bold;">By the end I’m usually suffering from information
overload and becoming brain-numb, but with 215 papers and an average of six
parallel sessions at any one time, plus the offsite events, that’s not really
surprising. On the other hand, where else do we go to get all this amazing
stuff?<o:p></o:p></span></div>
Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-64917844386369571392013-11-12T17:05:00.000-05:002013-11-12T17:12:31.620-05:00GLOBALFOUNDRIES to make Apple chips in New York fab?<div class="blogtitle">
I normally don't have the time to follow local press, but occasionally Google Alerts pops up with something quite interesting. In this case, the <a href="http://www.timesunion.com/" target="_blank">Albany Times Union</a> from Albany, New York had an <a href="http://blog.timesunion.com/business/globalfoundries-to-make-apple-chips-with-samsung/57805/" target="_blank">intriguing headline</a> that supports some of the gossip around Apple's fabrication plans for their A-series processor chips, <a href="http://electroiq.com/chipworks_real_chips_blog/2013/09/21/apple-a7-uses-samsungs-28nm-process/" target="_blank">up to now fabbed by Samsung</a>.</div>
<div class="blogtitle">
</div>
<div class="blogtitle">
At least in the short term, and from a technology point of view, this makes a lot more sense than Apple's much-vaunted switch to TSMC, since GLOBALFOUNDRIES (as part of the Common Platform alliance with Samsung) uses a gate-first HKMG process rather than TSMC's gate-last strategy. In fact, a couple of years ago GLOBALFOUNDRIES and Samsung <a href="http://www.globalfoundries.com/newsroom/2011/20110830_Samsung.aspx" target="_blank">announced that they were synchronizing their fabs</a> so that customers could transfer products from one foundry to the other without the pain of redesign.</div>
<div class="blogtitle">
</div>
<div class="blogtitle">
At the 20-nm node it might be different story, since all the foundries will be using gate-last processes; I can see TSMC picking up some of the business then, and there <em>are</em> persistent rumours of Apple trial lots going through TSMC.</div>
<div class="blogtitle">
</div>
<div class="blogtitle">
It also makes sense that GLOBALFOUNDRIES would make a pitch for the Apple work, since they are hungry for customers, and if they can get in at the 28-nm node they will be well positioned for 20-nm products in the next A-chip generations. Apple business would also help fill the potential second fab for which they have obtained outline planning permission in the <a href="http://www.lutherforest.org/index.php" target="_blank">Luther Forest Technology Campus</a>.</div>
<div class="blogtitle">
</div>
<div class="blogtitle">
When it comes to the processes, the 28-nm samples that we have seen from GloFo and Samsung are remarkably similar; this is a SEM cross-section of the transistors and first-level metal in the <a href="https://chipworks.secure.force.com/catalog/ProductDetails?sku=REL-RK3188&viewState=DetailView&cartID=&g=&parentCategory=&navigationStr=CatalogSearchInc&searchText=Rockchip" target="_blank">Rockchip RK3188</a> that Ajit Manocha announced at Semicon West:</div>
<div class="blogtitle">
</div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgLJNhHdRPDw9iP83pBO2j5i47xCjC2hCEAui5V8yKeGABHJM8P2gm80eJ4gYaZIl_z8r87DO-aRdBTIfFFQSCsdSI65pJ17yNnOJU4yx6s7vGyqGGxqDJOoYNsxuI4IJ8x_RoxTC9xpKMO/s1600/Rockchip+RK3188_branded.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgLJNhHdRPDw9iP83pBO2j5i47xCjC2hCEAui5V8yKeGABHJM8P2gm80eJ4gYaZIl_z8r87DO-aRdBTIfFFQSCsdSI65pJ17yNnOJU4yx6s7vGyqGGxqDJOoYNsxuI4IJ8x_RoxTC9xpKMO/s320/Rockchip+RK3188_branded.png" width="285" /></a></div>
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<div class="blogtitle">
Now let's look at a similar section out of a <a href="https://chipworks.secure.force.com/catalog/ProductDetails?sku=SAM-5410&viewState=DetailView&cartID=&g=&parentCategory=&navigationStr=CatalogSearchInc&searchText=Exynos">Samsung Exynos 5410</a> app's processor:</div>
<div class="blogtitle">
</div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh7kThJVf7BcVLqHThqp2of2WZzaKjY2Yd82eykrUk9Ta0y__qPuPgB6-x2degL_qCYeiCJytfMNIG11W3FEhJhUG-gVLXIsxRUwtqs5Xa0D_J_QJrU4Uf39h8klb2dBvoAjaFdCzdtX5HB/s1600/Samsung+Exynos+5410_branded.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="310" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh7kThJVf7BcVLqHThqp2of2WZzaKjY2Yd82eykrUk9Ta0y__qPuPgB6-x2degL_qCYeiCJytfMNIG11W3FEhJhUG-gVLXIsxRUwtqs5Xa0D_J_QJrU4Uf39h8klb2dBvoAjaFdCzdtX5HB/s320/Samsung+Exynos+5410_branded.png" width="320" /></a></div>
<div class="blogtitle">
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<div class="blogtitle">
There may be some very subtle differences that show up in very detailed analysis, but essentially they look pretty close; the fab synchronizing looks good to me!</div>
<div class="blogtitle">
</div>
<div class="blogtitle">
So the Times Union report may be just a blog rumour, but given the apparent compatibility of the two processes, it has the whiff of authenticity, and we may see A7s out of New York State in the not too distant future.</div>
<div class="blogtitle">
</div>
<div class="blogtitle">
Now, if we get one into Chipworks, can we tell the difference?</div>
Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-55634946107288000382013-09-21T16:32:00.000-04:002013-09-21T16:39:17.445-04:00Apple A7 uses Samsung’s 28-nm processLast week we started tearing down the Apple iPhone 5S. There has been much speculation that Apple would be moving their processor chips over to TSMC, but I think that we can now decisively say that this has not occurred - they have migrated to 28-nm, but still at Samsung.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiffwuyMy8HbpZNuoHi5Q16LVXUaw7SivPPvXbb2EP0vE7PX90PmdDYwB_tZ_7j1Rx5r-c1eEaKjslNjCffGC7VuWW89gGUhgyG3dhTbX5duVa2JHuJ-Wsp1N4LmGLXJzvEHqjyqaqnZr_b/s1600/APL0698_148137.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiffwuyMy8HbpZNuoHi5Q16LVXUaw7SivPPvXbb2EP0vE7PX90PmdDYwB_tZ_7j1Rx5r-c1eEaKjslNjCffGC7VuWW89gGUhgyG3dhTbX5duVa2JHuJ-Wsp1N4LmGLXJzvEHqjyqaqnZr_b/s320/APL0698_148137.jpg" width="301" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Apple's A7 Processor Die Image</td></tr>
</tbody></table>
<div class="separator" style="clear: both; text-align: center;">
</div>
Earlier in the day last Friday we established from the look of the die that the A7 was manufactured by Samsung. In the meantime our guys have been grafting away in the lab, and came to the “boring” conclusion that the chip looked exactly the same as the last one.<br />
<br />
The devil is in the details, however, and we have to do some measurements to see the difference.<br />
<br />
Below is a SEM image of a cross-section of a group of transistors in the A6 (APL0598) chip, fabbed in the Samsung 32-nm high-k-metal gate (HKMG) process. For convenience we have measured ten, so the dimension of the contacted gate pitch is 123 nm.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj7NpbcBI0Kttz6DB6iIXNGyhLL6n3VEEKM4qZAJgcgQMJ206fOQkKjXXj98h8vr0Nvefinon51CJDq-8oLsRa0o7O7rSs2orrRXqDEz2lT83YtFttpfNZF19l0LN7FzAgHsG7F0oAECmP5/s1600/551_CG+pitch+123+nm.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="258" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj7NpbcBI0Kttz6DB6iIXNGyhLL6n3VEEKM4qZAJgcgQMJ206fOQkKjXXj98h8vr0Nvefinon51CJDq-8oLsRa0o7O7rSs2orrRXqDEz2lT83YtFttpfNZF19l0LN7FzAgHsG7F0oAECmP5/s320/551_CG+pitch+123+nm.png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">SEM Cross-Section of Apple A6 (APL0598) Die</td></tr>
</tbody></table>
Now if we look at a similar image of the A7 (APL0698) below, and we see that the contacted gate pitch is 114 nm. So, even allowing for measurement error (we figure +/- 5%), we’re pretty sure that we see a shrink, and that the A7 is made on the same process as the new Samsung Exynos 5410, the 28-nm HKMG process.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj53XDQCBzC182oqMo_k29ZMVPnUtzjZ0HYZnkYIpDM1nKGUhmPd_imV0h1bVVLkSSFVGy7ra3fghCWdhLKy0kzaxYFnJGLJQhtkHhma4Z8AKgy-cc7ug9YzQIeLclE0BKO7UH-Tbh-qbgZ/s1600/367_SRAM_pitch_120nm_CG+pitch+114+nm.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="258" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj53XDQCBzC182oqMo_k29ZMVPnUtzjZ0HYZnkYIpDM1nKGUhmPd_imV0h1bVVLkSSFVGy7ra3fghCWdhLKy0kzaxYFnJGLJQhtkHhma4Z8AKgy-cc7ug9YzQIeLclE0BKO7UH-Tbh-qbgZ/s320/367_SRAM_pitch_120nm_CG+pitch+114+nm.png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">SEM Cross-Section of Apple A7 (APL0698) Die</td></tr>
</tbody></table>
That doesn’t sound much, a mere 4 nm, but again if you do the math and remember that we’re talking area shrink, not linear dimensions, then 28^2 divided by 32^2 (784/1024) comes out at about 77% of the area for the equivalent functionality. Or, given that the A7 is 102 mm^2 compared with 97 mm^2 for the A6, more functions in a slightly bigger area.<br />
<br />
Below is a delayered sample of the A7, but we have yet to identify what that functionality is, something that we will be doing in the next few weeks.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjYVFqzN-RQGdn_xj9KD0NACYRJXEHU9OGQRcFx63cDGrVxBSe2dSmq36UxDq6xzJbPreeAQLNt33OMN5hqTkGDjlRVz2pudWzoHP7jEbAVxWZDkgNU1jiZuy-P3LwZMwhWIruwf3evezdv/s1600/APL0698_148138_PolyB.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjYVFqzN-RQGdn_xj9KD0NACYRJXEHU9OGQRcFx63cDGrVxBSe2dSmq36UxDq6xzJbPreeAQLNt33OMN5hqTkGDjlRVz2pudWzoHP7jEbAVxWZDkgNU1jiZuy-P3LwZMwhWIruwf3evezdv/s320/APL0698_148138_PolyB.jpg" width="299" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Transistor-Level Image of the Apple A7</td></tr>
</tbody></table>
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<br />Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-2292419812761067622013-07-29T16:48:00.001-04:002013-08-06T11:04:53.211-04:00Qualcomm Snapdragon 800 and Rockchip RK3188 - Battle of the Foundries!<div style="text-align: left;">
The <a href="http://www.qualcomm.com/snapdragon/processors/800" target="_blank">Snapdragon 800</a> (<a href="https://chipworks.secure.force.com/catalog/ProductDetails?sku=QUA-MSM8974&viewState=DetailView&cartID=&g=&parentCategory=&navigationStr=CatalogSearchInc&searchText=FAR-1306-801" target="_blank">Qualcomm MSM8974</a>)<span class="Apple-style-span" style="font-size: 13px;"> </span>is Qualcomm’s leading-edge, low-power, mobile phone app’s processor with built-in 3G/4G LTE modem, using the latest Krait 400 CPU rated at 2.3 GHz and their 450 MHz Adreno 330 GPU. It was launched at this year's CES International with <a href="http://www.youtube.com/embed/N9Y_naTHPsY?feature=player_embedded" target="_blank">this rather slick commercial</a>.<br />
<br />
Significantly, it is fabricated using the <a href="http://www.tsmc.com/english/dedicatedFoundry/technology/28nm.htm" target="_blank">TSMC 28HPM</a> (28-nm, High-Performance Mobile) process, which extends TSMC’s high-k, metal gate (HKMG) processing into the mobile space. Before this, all Qualcomm’s mobile chips were made with the TSMC 28LP polysilicon gate/SiON process; and to our knowledge, this is the first volume production part using 28HPM.<br />
<br />
The 28HPM process sees a shrink in minimum gate lengths and SRAM cell size when compared with the 28HP process, and the inclusion of embedded SiGe source/drains for PMOS strain, which was not part of 28HPL.<br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgdipxBC-uO9O9lapb5-JcrgeQ8iIFdbWvtBehpr_QFsi97vVcv3QWTnLEo4TR_yaFCpRo3V7cBZuQfxtKNDPY69SA-Z5x3E8L4lacp6-PW0Hq1F7s0Vo6w9Sp0Ca4-BGsywT1b9aPNstou/s1600/TSMC+28HPM+PMOS.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgdipxBC-uO9O9lapb5-JcrgeQ8iIFdbWvtBehpr_QFsi97vVcv3QWTnLEo4TR_yaFCpRo3V7cBZuQfxtKNDPY69SA-Z5x3E8L4lacp6-PW0Hq1F7s0Vo6w9Sp0Ca4-BGsywT1b9aPNstou/s320/TSMC+28HPM+PMOS.png" width="319" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">TSMC 28HPM PMOS transistor</td></tr>
</tbody></table>
TSMC claims the technology can provide better speed than 28HP while giving similar leakage power to 28LP. The wide performance/leakage coverage apparently makes 28HPM ideal for applications from networking, tablet, to mobile consumer products.<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiaCxY9UpNaFQXRjqzo6ThLkFwX63oB5TiY91N6-LL5VWSOO-hU9IUyIEeWfZb0APGMplDCMSVR-3H5lO5J3pAphLMgVd54gzpUHNDDW4cHAPD2Zd5vmKqLLq4o34r20qHNXtZw0sgoeauP/s1600/TSMC+28HPM.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="193" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiaCxY9UpNaFQXRjqzo6ThLkFwX63oB5TiY91N6-LL5VWSOO-hU9IUyIEeWfZb0APGMplDCMSVR-3H5lO5J3pAphLMgVd54gzpUHNDDW4cHAPD2Zd5vmKqLLq4o34r20qHNXtZw0sgoeauP/s320/TSMC+28HPM.png" width="320" /></a></div>
<br />
<br />
The <a href="http://www.rock-chips.com/index.php?do=news&id=158" target="_blank">Rockchip RK3188</a> is targeted on tablets rather than phones, but it uses the <a href="http://www.globalfoundries.com/technology/28nm.aspx" target="_blank">GLOBALFOUNDRIES’ 28SLP</a> (Super Low Power) process, their equivalent to TSMC’s 28HPM, aimed at mobile products. It is again a quad-core part, this time with ARM A9 CPUs running at 1.6 GHz, and quad-core ARM Mali GPUs rated at 600 MHz.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZcHw1FIS5argm-4GpkeaqfGJn9aklDbVseon-YfeeS86Smv4k_KlquR9_QOasBHLmXzHzzrmstIhO9V0HxJTjhIBh5eYz9kCDBrBS1v7AKQXy61m5ctHt-kiBZm_r6d22kosEtyvrqWIx/s1600/Rock+3188.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZcHw1FIS5argm-4GpkeaqfGJn9aklDbVseon-YfeeS86Smv4k_KlquR9_QOasBHLmXzHzzrmstIhO9V0HxJTjhIBh5eYz9kCDBrBS1v7AKQXy61m5ctHt-kiBZm_r6d22kosEtyvrqWIx/s320/Rock+3188.png" width="262" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><a href="https://chipworks.secure.force.com/catalog/ProductDetails?sku=REL-RK3188&viewState=DetailView&cartID=&g=&parentCategory=&navigationStr=CatalogSearchInc&searchText=REL-RK3188" target="_blank">Rockchip RK3188</a> floorplan showing some of the major functional blocks</td></tr>
</tbody></table>
Rockchip has squeezed the functionality into ~25 sq. mm, less than a quarter of the size of the Qualcomm chip; not least because the A9 cores are noticeably smaller than the Qualcomm-designed Krait cores based on the ARM architecture, and of course there is no LTE.<br />
<br />
GLOBALFOUNDRIES is obviously happy to have won the Rockchip business – <a href="http://www.youtube.com/embed/cog-DF5r3YE?feature=player_embedded" target="_blank">their CEO Ajit Manocha specifically mentioned</a> the partnership in his <a href="http://semiconwest.org/SessionsEvents/Keynotes" target="_blank">keynote</a> talk at Semicon West:<br />
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The 28SLP process differs in a basic way from the TSMC 28HPM – GloFo is using their version of the <a href="http://www.commonplatform.com/" target="_blank">Common Platform</a> (GLOBALFOUNDRIES, IBM, Samsung) 28-nm process, which is a ‘gate first’ variety, i.e. a polysilicon gate is used with a HKMG stack at its base, doped to form NMOS and PMOS transistors. TSMC's ‘gate last’ process uses a sacrificial polysilicon gate for all the processing up to the end of the source/drain processing, then the polysilicon is removed and replaced with distinct HKMG stacks which are tuned for NMOS and PMOS.<br />
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Like the other Common Platform HKMG processes, a SiGe channel is used in the PMOS transistors, though with GloFo’s own spin – none of these processes are the same from the different vendors. <br />
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Compared with the older 32-nm HKMG process used for AMD processors, the Rockchip uses bulk silicon, not SOI, and gate lengths, contacted gate pitches and SRAM cell size are shrunk, but in the same ballpark as TSMC’s process. There is no dual-stress liner or embedded SiGe source/drains to enhance PMOS performance, but this product is rated at 1.8GHz rather than TSMC/Qualcomm’s 2.3 GHz. <br />
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<tr><td class="tr-caption" style="text-align: center;">GLOBALFOUNDRIES 28SLP PMOS transistor</td></tr>
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So we have two processes targeted at similar spaces, but with very different takes on how to do it. TSMC and Qualcomm are following the industry norm, supplying chips to a US company from Taiwan, and GLOBALFOUNDRIES and Rockchip have reversed the trend, supplying chips to China from the West, and it's tempting to speculate they are from the Malta fab in New York.
Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-40927571475533467282013-07-11T14:22:00.000-04:002013-07-15T10:00:05.636-04:00A Dispatch from SEMICON West – Applied Materials Launches Epi System Focused on NMOS StrainFlying in to SFO on July 7, I must have been one of many attendees delayed by the after-effects of the <a href="http://abcnews.go.com/US/san-francisco-plane-crash-pilot-43-hours-flying/story?id=19598352" target="_blank">Asiana Airlines crash</a> there the day before. In my case it was only an hour or so (i.e. as normal), but we couldn’t avoid seeing the remains of the aircraft as we landed. Despite the fact that the plane was burnt out, I couldn’t help being impressed that the main body of the plane had survived the impact, and of course all but two of the passengers survived – and they were outside the plane.<br />
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By coincidence I flew through Heathrow a week after another 777 did a belly-flop there a few years ago, and again I was impressed at the strength of the airframe – an engine had been ripped off a wing but otherwise it was pretty well intact – and fortunately in that case there was no fire, and no fatalities.<br />
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That’s hardly relevant to SEMICON West of course, but it’s hard not to get involved when we get that close to the statistics of travel accidents, be they road, rail or air.<br />
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Anyway – back to the show – or at least the pre-show events. Applied Materials (AMAT) had an analyst day on Monday, and in the morning they invited a few of us to some product launches. The one that caught my eye and ear was <a href="http://www.appliedmaterials.com/newsroom/news/applied-materials-unveils-new-epitaxy-technology-high-performance-transistors" target="_blank">a new epi system focused on NMOS</a> epitaxial source/drains to create channel strain, since that has been mooted as a next step for several years now, but not shown up in a production context.<br />
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The theory is that if you can get carbon and phosphorus to replace silicon atoms in the crystalline structure, because they are smaller than silicon, they will generate tensile stress in the crystal lattice. When it is deposited in cavities etched in source/drains the stress is applied to the channel. (Putting the larger germanium atoms in the lattice has the opposite effect, and creates compressive stress, an effect used since the 90nm node.)<br />
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<tr><td class="tr-caption" style="text-align: center;">Schematic of e-SiGe in PMOS (left), and e-Si:CP in NMOS (right) source/drains</td></tr>
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The problem (as I understand it) has been that the carbon does not like staying in such substitutional positions, and it will abandon them as soon as it sees anneal temperatures, thus losing the stress effect. Phosphorus is happy to be substitutional, and has of course been used as a n-type dopant for decades, so I suspect the problem there is simply getting the concentration to a level sufficient to stress the lattice.<br />
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So on Monday AMAT launched the <a href="http://www.appliedmaterials.com/technologies/library/centura-rp-epi" target="_blank">Applied Centura RP Epi system</a> with an NMOS transistor application. To quote: “This capability supports the industry's move to extend epi deposition from PMOS transistors to NMOS transistors at the 20nm node, enabling chipmakers to build faster devices and deliver next-generation mobile computing power.”<br />
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The Applied folks seem confident that once the epi is formed, the carbon can be kept stable and capable of applying the strain at the end of the manufacturing process. I quizzed them as to how this is done and apparently the keys are the quality of the clean after cavity etch (i.e. AMAT’s Siconi dry clean), plus millisecond annealing to minimize the thermal budget.<br />
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There is plenty of literature documenting the effect; at last year’s <a href="http://www.his.com/~iedm/" target="_blank">IEDM</a> conference, IBM announced their 22nm server process, which uses embedded strain for both N- and P-MOS[1]. Together with nitride stress, they claim a 10 percent performance increase over the 32nm equivalent. I also asked the speaker there about the carbon stability, and he confirmed that they regard it as a manufacturable process.<br />
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<tr><td class="tr-caption" style="text-align: center;">Cross-section of NFET showing embedded Si:C Source/Drain Stressor [1]</td></tr>
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It seems the time of e-Si:CP NMOS is here. Applied certainly hopes so: they estimate the available market at over $500M and expanding, and that revenue has doubled over the last five years, and they have more than 80 percent share. They see an incremental $250M in revenue from epi systems by 2016.<br />
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I’ve been waiting for epi-strained NMOS for the last couple of process generations, and had almost been convinced that it wouldn’t happen. Now we have to watch for it when we get the next 20nm parts!<br />
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[1] S. Narasimha et al., “22nm High-Performance SOI Technology Featuring Dual-Embedded Stressors, Epi- Plate High-K Deep-Trench Embedded DRAM and Self-Aligned Via 15LM BEOL”, IEDM 2012, pp 52 – 55.Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-75980474246635925732013-06-06T16:07:00.000-04:002013-06-10T09:21:39.008-04:00Economy Threatens Semi Growth, not Technology – so Say Fab Engineers at ASMCIt’s still spring in the north-eastern part of North America, and that means it’s the time of year for the Advanced Semiconductor Manufacturing Conference, in the amiable ambiance of Saratoga Springs, New York. The conference took place last month, on May 13 – 16.<br />
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As the name says, ASMC is an annual conference focused on the manufacturing of semiconductor devices; in this it differs from other conferences, since the emphasis is on what goes on in the wafer fab, not the R&D labs, and the papers are not research papers. After all, it’s the nitty-gritty of manufacturing in the fab that gets the chips out of the door, and this meeting discusses the work that pushes the yield and volumes up and keeps them there.<br />
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I always come away impressed by the quality of the engineering involved; not being a fab person myself any more, it’s easy to get disconnected from the density of effort required to equip a fab, keep it running and bring new products/processes into production. Usually the guys in the fab only get publicity if something goes wrong!<br />
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There were 81 papers spread over the three days, with keynotes from Subi Kengeri of GLOBALFOUNDRIES, Vivek Singh and Tim Hendry of Intel, and Bill McClean of IC Insights, and also a panel discussion on the benefits/pitfalls of 450mm wafers. This latter is particularly apposite here in Saratoga Springs since we have the Global 450 Consortium building their new fab at CNSE in Albany, just down the road from here. <br />
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The conference kicked off with Subi Kengeri’s keynote – “Assessing the Threats to Semiconductor Growth: Technology Limitations versus Economic Realities” – essentially, will Moore’s law run out of steam before or after chips get too expensive to sell?<br />
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<tr><td class="tr-caption" style="text-align: center;">Subi Kengeri of GLOBALFDOUNDRIES giving the opening keynote at ASMC</td></tr>
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On the one hand, we anticipate huge growth in revenue on the back of the mobile industry, with the foundries expected to outpace the overall industry, and leading-edge revenue doubling in the next five years:<br />
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And we know that technologically we can get to 14nm or even 10nm with multiple patterning, finFETs, etc., and possibly new materials.<br />
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On the other hand, SoC designs are getting larger, faster, and more complex, and wafer fab costs are going up, with lithography being the biggest component. (It’s worth noting here that at the 20nm generation, the middle-of line (MOL) processing separates from the back-end of line (BEOL), since the 1X interconnect level has to be double-patterned.)<br />
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This increased design and fab complexity also adds to development time and increases the time-to-volume (TTV), adding a time cost and reducing the return on investment. This could conceivably get the industry into a feedback loop, since TTV delay slows down industry growth, which slows downs investment, which slows down development, which slows down TTV.<br />
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The other obvious effect is the industry consolidation which we’ve all been part of – according to Subi only four companies will be fabbing at the 14nm node:<br />
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I had wondered why IBM wasn’t on the list until I saw the 50K wafers/month cut-off; even with all the games chips that IBM has churned out over the last few years, I doubt that IBM has hit that number.<br />
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If the predictions are correct, by 2016 28nm and below will make up 60 percent of the foundry market, split between four companies (or three, if Intel’s foundry ambitions don’t work out). That thought raised the prospect of capacity limitations, and gave Subi a chance to promote GLOBALFOUNDRIES as the only one of the three with a global footprint, and not in geographically or politically risky zones. <br />
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He finished his talk by identifying critical growth enablers for the industry as optimized SoC technology architecture (with a focus on techno-economics), coupled with true collaborative R&D, and of course the global footprint. And he also asked all of us in the room which was the biggest threat to growth – technology scaling limits, or the economic realities? Being techies, we all know that the next few generations are within sight technically, so we all voted for the economic problems – the part we can’t control!<br />
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<tr><td class="tr-caption" style="text-align: center;">The final vote</td></tr>
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As you can see, the vote was pretty overwhelming.<br />
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N.B. All images courtesy of GLOBALFOUNDRIES.Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-6253284924595755492013-01-30T15:40:00.000-05:002013-01-30T16:05:06.966-05:00Intel Foundries MEMS for Fuel Cell Start-up NectarIn the last couple of years there have been announcements that Intel will be acting as a foundry for FPGA company <a href="http://www.achronix.com/wp-content/uploads/pr/2010_Nov_Intel.pdf" target="_blank">Achronix</a>, PLD maker <a href="http://www.achronix.com/wp-content/uploads/pr/2010_Nov_Intel.pdf" target="_blank">Tabula</a> and programmable network processor provider <a href="http://www.netronome.com/pages/040412/" target="_blank">Netronome</a>, as well as much speculation about making chips for Apple. <br />
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All these reports refer to using Intel’s leading-edge 22-nm tri-gate process. However, at <a href="http://www.cesweb.org/About-CES.aspx" target="_blank">CES</a> a couple of weeks ago, my eye was caught by a 200-mm wafer on display at the booth of a little company called <a href="http://www.nectarpower.com/" target="_blank">Nectar</a>, who were pitching their fuel-cell based USB charging system. They claim that the charger can top up an iPhone battery at least ten times before the fuel pod has to be changed. The whole device can be held in one hand:<br />
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<tr><td class="tr-caption" style="text-align: center;">Fig. 1 Nectar fuel-cell charger (at right) on display at CES</td></tr>
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The cell uses butane fuel in a silicon-based power cell, and by the look of the image below the cells are ~22 mm square. </div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh8gvBF9TjIzBgmJky5lGfRd3hlppCQxTI7L6XjhKoleYdfjWWQevzecg1kzYNcU4XgglfsyCMTx0sGLoZAxzwxUQkAeYEDUkGasYQydYT8gOJhj8ZvAARmufXmPDKgCwZgBbUoebBvuCl7/s1600/Nectar_2.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh8gvBF9TjIzBgmJky5lGfRd3hlppCQxTI7L6XjhKoleYdfjWWQevzecg1kzYNcU4XgglfsyCMTx0sGLoZAxzwxUQkAeYEDUkGasYQydYT8gOJhj8ZvAARmufXmPDKgCwZgBbUoebBvuCl7/s320/Nectar_2.png" width="279" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Fig. 2 Nectar MEMS wafer on display at CES</td></tr>
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The press pack given out at the show includes a paper [1] with a description of the technology; a solid oxide fuel cell (SOFC) is used, which is compatible with silicon processing. I’m not a fuel cell expert, so to quote from the paper: <br />
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"Fuel cells operate by creating opposing gradients of chemical concentration and electrical potential. When an ion diffuses due to the concentration gradient, the associated charges are transported against the electric field, generating electrical power. In the case of SOFCs, the mobile ion is O2-, and the oxygen gradient is created by providing air on one side (the cathode) and a fuel mixture which consumes any free oxygen on the other side (the anode). Any fuel which burns oxygen will produce power in an SOFC." The schematic below (Fig. 3) illustrates the process. <br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg6NFLho8rVHEUbm7FjYcJXoJTsuF5tq1Uo-ywwxnQs204BXHvSMAZ_C9C_d2l5Z7xe2emxDi67Szf3tJY9isXqguLwVMEJPV47nQ0otzNGX6EqdqTtgy-j_9oKEBE4Mf7s1bQcLjWScwMO/s1600/Nectar_3.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="235" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg6NFLho8rVHEUbm7FjYcJXoJTsuF5tq1Uo-ywwxnQs204BXHvSMAZ_C9C_d2l5Z7xe2emxDi67Szf3tJY9isXqguLwVMEJPV47nQ0otzNGX6EqdqTtgy-j_9oKEBE4Mf7s1bQcLjWScwMO/s320/Nectar_3.png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Fig. 3 Operating principle of solid oxide fuel cell</td></tr>
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The butane has to be cracked so that hydrogen is available, which is done in a "fuel processor" within the cell. The following diagram shows the sequence of power generation [1]. <br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi8twRML6Pk_10oNcb1otTomtBnKXu6n_N0AKMpzy0FXr3exvaiMr-f__Tyscdy16sQFJ3WHhB4aUUdq5NsME-cHnBfcaCaXLZfF9uxsIbGk8blhVu6-KIGjE_hQFIP3gHicHTDIK2Bl5aA/s1600/Nectar_4.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="111" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi8twRML6Pk_10oNcb1otTomtBnKXu6n_N0AKMpzy0FXr3exvaiMr-f__Tyscdy16sQFJ3WHhB4aUUdq5NsME-cHnBfcaCaXLZfF9uxsIbGk8blhVu6-KIGjE_hQFIP3gHicHTDIK2Bl5aA/s320/Nectar_4.png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Fig. 4 Diagram of fuel cell power generator</td></tr>
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The Nectar generator chip contains the fuel processor, fuel cell stack, and catalytic converter. The fuel processor cracks the butane into hydrogen and carbon monoxide by using a lean mixture of air and butane to give incomplete combustion; then O2- ions from the air feed on the other side of the SOFC stack migrate through the stack and combine to give water and carbon dioxide; then the exhaust gases exit through a catalytic converter. <br />
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It is here that the MEMS structure comes in – even incomplete combustion of the butane gives temperatures of 600 – 800C, so to integrate this into a package that can be carried around, and also must have conventional silicon for power conditioning has to be a challenge. The fuel processor uses a mechanically suspended reaction zone formed in silicon, with a heat exchanger adjacent to the reaction zone, as shown in Fig. 5 [1, 2]:<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhJ6bohhYsddljhnq3mRlVbPIFo4W8oedx2RF6VmvexVj3wq-zowtnDjrXmYW2x9oP39B_2HgMaDLs6Nv_sStYN05_rSZYgXUz-MHJxtHs-Xb4co1xtELpqw7-DTK3GNuAsm5SRp5MI5hhM/s1600/Nectar_8.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhJ6bohhYsddljhnq3mRlVbPIFo4W8oedx2RF6VmvexVj3wq-zowtnDjrXmYW2x9oP39B_2HgMaDLs6Nv_sStYN05_rSZYgXUz-MHJxtHs-Xb4co1xtELpqw7-DTK3GNuAsm5SRp5MI5hhM/s320/Nectar_8.png" width="268" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Fig. 5 Experimental (top) and later (bottom) MEMS fuel processor</td></tr>
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The nitride tubes contain the gas stream, while the silicon bars provide the heat transfer from the exit stream to the input stream. Fig. 6 shows the modeled heat transfer in a pair of tubes (red = hot, blue = cool) [1]. The U-bend at the end is the reaction zone; ignition is started using a platinum heater deposited on the surface, and once started continues autothermally. <br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiTbmgbLJ3tNfrIRFrBc42ICKbyDbVmgAclEpp1zhlUM_sNTIocqfowRvVtpBZBU2qdEOMqMjeK3BTnW337E9OV_5V9CynyTh_tcOlxArYHdYHoa0ETLGNrL2-ikArG0zRydgknOGf_9Zh9/s1600/Nectar_9.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="227" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiTbmgbLJ3tNfrIRFrBc42ICKbyDbVmgAclEpp1zhlUM_sNTIocqfowRvVtpBZBU2qdEOMqMjeK3BTnW337E9OV_5V9CynyTh_tcOlxArYHdYHoa0ETLGNrL2-ikArG0zRydgknOGf_9Zh9/s320/Nectar_9.png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Fig. 6 Schematic of modeled heat recovery in reaction loop</td></tr>
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The SOFC itself is built of yttrium-stabilized zirconium oxide (YSZ) plates held in a nitride matrix, supported on silicon walls. In order to keep the profile as slim as possible a "planar stack" of plates is formed as shown schematically in Fig. 7(a), with the detail of a single plate in Fig 7(b)[1].<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg6-mIrpz_EvVBd7UcEzS7J0Fq8Q7Pjnb24gsVYAnScdPuj3mj3UvZURhfqhmZHJqvr7sfGLIPo9oaqky91BfWNdHNtHNyw2uBodT1oP0dPjr-cKKFoJlMvsGlzWek3_7-8CEvP1In7nJHd/s1600/Picture1.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg6-mIrpz_EvVBd7UcEzS7J0Fq8Q7Pjnb24gsVYAnScdPuj3mj3UvZURhfqhmZHJqvr7sfGLIPo9oaqky91BfWNdHNtHNyw2uBodT1oP0dPjr-cKKFoJlMvsGlzWek3_7-8CEvP1In7nJHd/s320/Picture1.png" width="281" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Fig. 7 (a) Schematic of SOFC plates and (b) Cross-section of single cell</td></tr>
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Details of the anode and cathode materials are not given, but they clearly have to be porous to allow the gases to diffuse through and react. Similarly nothing is said about the catalytic converter, but that also should be compatible with MEMS manufacturing. <br />
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The inherent ability of MEMS processes to provide vacuum-sealed structures helps contain the heat generated within the system, and the chamber is lined with reflective shielding to further reduce heat losses. Even so a new sealing glass had to be developed, since the conventional lead-glass frits used in many MEMS devices was not up to the job. <br />
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The whole assembly is packaged in a “tin can” with the gas inlets and exits on the reverse side of the package: <br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgFTSistauiFUmzJVg-KaDF4U2c7U7csPOLV8WpS8s_XXnBcT815RvqPaCUOzk9RxTjydTg05qbohYMxM-zlSo7R-2gKM8raSaO2ZgxsDLgBp7Arq0xmFy2mBtT-a2h6PdgS0igF5jNUaw6/s1600/Nectar_5_branded.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="251" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgFTSistauiFUmzJVg-KaDF4U2c7U7csPOLV8WpS8s_XXnBcT815RvqPaCUOzk9RxTjydTg05qbohYMxM-zlSo7R-2gKM8raSaO2ZgxsDLgBp7Arq0xmFy2mBtT-a2h6PdgS0igF5jNUaw6/s320/Nectar_5_branded.jpg" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Fig. 8 Assembled and packaged Nectar fuel cell</td></tr>
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Of course, smart as the fuel cell manufacturing is, it is only part of a charging system. Fig 9 [1] is a block diagram of the whole system, showing the peripheral components needed to complete the unit and turn it from a concept into a functioning charger. The battery allows power to be drawn instantaneously from the charger while the fuel cell fires up, and also powers the supporting components. <br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgpEhxjYnaJyMHGghYmnXWduSRrkE3voZL2tBz_oYDedPzaxWxT-luaxKIzOzKkmtJkLQDk5AcmgKWCkNfKVMLVPz09Vjiy_fNlw2QXGYQj4Hgfygop6IuhMzB3eC610dPJK3rp8ZPP_6bZ/s1600/Nectar_13.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="217" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgpEhxjYnaJyMHGghYmnXWduSRrkE3voZL2tBz_oYDedPzaxWxT-luaxKIzOzKkmtJkLQDk5AcmgKWCkNfKVMLVPz09Vjiy_fNlw2QXGYQj4Hgfygop6IuhMzB3eC610dPJK3rp8ZPP_6bZ/s320/Nectar_13.png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Fig. 9 Block diagram of Nectar fuel-cell charging system</td></tr>
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I started this blog off by talking about Intel, then veered off into a description of the Nectar charger – what was I babbling about? Well, when I was looking at the charger at CES I had a word with Sam Schaevitz of Lilliputian Systems, which developed the Nectar, and asked him who made the MEMS, expecting to hear about of one of the MEMS foundries that are around. (Lilliputian is a spin-off of MIT – Sam is founder and CTO.) <br />
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Much to my surprise, he answered "Intel"! As I said at the beginning, there has been quite a bit of comment about Intel moving to the foundry model, but nothing about them being in the MEMS business. It turns out that the work is done at Intel’s fab in Hudson, Mass., which those with long memories will recall was the DEC fab bought by Intel when DEC went under back in 1998. <br />
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I had assumed that it would have been closed long ago, but Intel claims to have put $2B into the plant, converting it to 130 nm back in 2001, and it’s now known as Fab 17. It is now Intel’s sole remaining 200 mm facility. In addition they have their Massachusetts Microprocessor Design Center and the Massachusetts Validation Center on the same site, employing ~1700 in total. <br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhYXmcvIUkMwwKbbXslnixinrcMfhHYOL4TrCRWNxyhRH89ZjhRYnqRGHQthTjkIbkZsiJcTVjbA8A23e6ep2O5SnzTI2MmipHT-NA3YLRTKULoOOdNVjGdhghvToPeh7Z7A1w3I2XnKlWQ/s1600/Fab17.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="160" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhYXmcvIUkMwwKbbXslnixinrcMfhHYOL4TrCRWNxyhRH89ZjhRYnqRGHQthTjkIbkZsiJcTVjbA8A23e6ep2O5SnzTI2MmipHT-NA3YLRTKULoOOdNVjGdhghvToPeh7Z7A1w3I2XnKlWQ/s320/Fab17.jpg" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Fig. 10 Intel’s Fab 17 in Hudson, MA (source: Intel)</td></tr>
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Intel’s <a href="http://www.intel.com/content/dam/www/public/us/en/documents/fact-sheets/standards-global-manufacturing-facts.pdf" target="_blank">Global Manufacturing Fact Sheet</a> states that the fab manufactures “chipsets and other” – the Nectar chip is clearly an “other”! Nectar <a href="http://www.nectarpower.com/media/wafer-agreement-with-intel-and-equity/" target="_blank">announced</a> their supply link with Intel back at the end of 2010, but I missed it at the time; Intel Capital also has a stake in Lilliputian.<br />
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Aside from the regular processing equipment, Intel must have invested in deep RIE etchers, never mind the deposition gear capable of forming YSZ and the other exotic materials likely used for the anode/cathode and catalytic converter. Presumably Intel’s need for 130-nm chipsets is slowly fading; this looks like a praiseworthy way of keeping the fab going, as well as supporting a local start-up – and one wonders what other foundry work is going on there. If you do have the urge to buy a Nectar mobile power system, it will be available through <a href="http://www.brookstone.com/nectar-mobile-power-system" target="_blank">Brookstone</a> in the summer.<br />
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References:<br />
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[1] S. Schaevitz, <em>Powering the wireless world with MEMS</em>, Proc. SPIE 8248, Micromachining and Microfabrication Process Technology XVII, 824802 (February 9, 2012) <br />
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[2] L. Arana et al., <em>A Microfabricated Suspended-Tube Chemical Reactor for Thermally Efficient Fuel Processing</em>, J. MEMS 12(5) 600-612Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com1tag:blogger.com,1999:blog-5488132572864585098.post-32669306616002215162012-12-11T13:54:00.001-05:002012-12-11T17:00:45.393-05:00IBM surprises with 22nm details at IEDMMonday afternoon at the 2012 <a href="http://www.his.com/%7Eiedm" target="_blank">IEEE International Electron Devices Meeting</a>, IBM discussed their 22nm SOI high-performance technology [1], aimed at servers and high-end SoC products. To an extent, this is an extension of the 32nm process, using epitaxial SiGe for the PMOS channels and stress, and dual-stress liners for both NMOS and PMOS strain. However, there were a couple of surprises buried in there -- at least for me!<br />
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The first surprise was that this is a gate-first process, contrary to the announcements made by the Common Platform group that the 20nm class processes would be gate-last. The difference seems to be that this technology <i>IS</i> aimed at high performance servers and their support devices, not consumer products, and this is IBM's process for its high-end products, so they are sticking with the proven formula and pushing it to the next level.<br />
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The gate dielectric stack has been scaled to reduce the inversion thickness (t<sub>inv</sub>) by 7%/10% (NMOS/PMOS), without affecting mobility, modifying the clean, depositions (using ALD for the interfacial oxide), and anneal steps to achieve the lowest t<sub>inv</sub> published so far, and reducing DIBL by 6%/8%.<br />
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The second surprise was that e-Si:C (embedded carbon-doped source/drains) has been used for NMOS stress -- IBM claimed that this is the first time in a production process. I had just about written e-Si:C off as a viable manufacturing technique, since I've been hearing over the last few years that the carbon is not stable and does not stay in the substitutional crystalline sites where it's needed. However, here we are told that it is stable and that it survives all the backend processing, even with the 15 layers of metal used in this technology.<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgH7ishkK9k7QKTA-9TIOQ8JoVfGrM62z3hjoklc_VNBsHeFv4AFLkwUaydtoBPpmi9ENXRbwvlvYvxtnSDW_CHZhAPMQto2svgjKRjEHInhB46DANmbbh5jYBLBH7Shyphenhyphendvq10_42S0vEjh/s1600/Fig+4.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="276" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgH7ishkK9k7QKTA-9TIOQ8JoVfGrM62z3hjoklc_VNBsHeFv4AFLkwUaydtoBPpmi9ENXRbwvlvYvxtnSDW_CHZhAPMQto2svgjKRjEHInhB46DANmbbh5jYBLBH7Shyphenhyphendvq10_42S0vEjh/s400/Fig+4.png" width="400" /></a></div>
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<i><b>Fig. 1:</b> TEM cross-sections of e-SiGe in PFET (left), and e-Si:C in NFET</i> [1]</div>
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The e-Si:C incorporates ~1.5% C, which combined with fourth-generation e-SiGe with more Ge and the dual-nitride stress liners, gives 25% more strain than the 32nm process.<br />
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The gate-first approach allows conventional contacts and self-aligned silicide, and judging by <b>Fig. 3</b>, raised source/drains help to reduce S/D resistance and keep the gate/contact capacitance under control.<br />
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The embedded trench DRAM is not a surprise, IBM has a long history in the field and they have now brought it to the point where access time is shorter than SRAM [2, 3, 4].<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj0p9VSQYJWyd0w69c7AXX4M1oJMzV8w32Bfzf8DXDhNodiRlQZuX34RnRxDejJGGx6PXIIQhScTwxKFuIZtsf9A2eODiPUNO9roodXauaSwgcGhJUBZJ9xWf2wMZ18739wuDK-KlG9UEAl/s1600/Fig+5.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="300" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj0p9VSQYJWyd0w69c7AXX4M1oJMzV8w32Bfzf8DXDhNodiRlQZuX34RnRxDejJGGx6PXIIQhScTwxKFuIZtsf9A2eODiPUNO9roodXauaSwgcGhJUBZJ9xWf2wMZ18739wuDK-KlG9UEAl/s400/Fig+5.png" width="400" /></a></div>
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<i><b>Fig. 2:</b> IBM roadmap for e-DRAM</i> [2]</div>
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The big change here is that the substrate wafer has an N+ epi layer on it to replace the diffused cell plate of earlier generations. This allows denser packing, since a formerly-needed diffused spacer is removed, giving a cell size of 0.026 μm<sup>2</sup>. It also enables deeper trenches, giving higher cell capacitance for an areal capacitance of 280 fF/ μm<sup>2</sup>. The trench capacitors are also used as decoupling capacitors, and these are isolated by deep trench isolation so that they can be biased independently.<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjqg8YVrLfk3r3W7GuGTGlL_7-k19M5H2s9nGhBQRMj8D4K3JNQNiPH3YqMJchhyphenhyphen8FFMAgabk141CmeZpF3FyXpd0v440TR5IIGYLlegs2QFczfCXLLxRCtzFmef5z7emGOL4h-GItfSolE/s1600/Fig+6.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="283" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjqg8YVrLfk3r3W7GuGTGlL_7-k19M5H2s9nGhBQRMj8D4K3JNQNiPH3YqMJchhyphenhyphen8FFMAgabk141CmeZpF3FyXpd0v440TR5IIGYLlegs2QFczfCXLLxRCtzFmef5z7emGOL4h-GItfSolE/s400/Fig+6.png" width="400" /></a></div>
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<i><b>Fig. 3:</b> (left) SEM cross-section of e-DRAM trench capacitors; (right) plan-view and <br />cross-section schematics of decoupling and isolation trenches, showing N+ epi plate</i> [1]</div>
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(As an aside, one of the comments from Greg Taylor of Intel in his microprocessor talk in Sunday's <a href="http://www.electroiq.com/articles/sst/2012/september/iedm-unveils-2012-program-highlights.html" target="_blank">IEDM short course</a> was that the analog functions that are part of a CPU are getting more significant as dimensions shrink. Both Intel and IBM are now using on-chip decoupling capacitors; Intel with MIMCAPs, and IBM with trench capacitors.)<br />
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The complexity of IBM's server chips is reflected in the 15 levels of metal. The first level is doubled-masked with a litho-litho-etch sequence to allow for orthogonal layout; the rest are single-patterned using uni-directional layout. Self-aligned vias help with packing, and both ultralow-<i>k</i> and low-<i>k</i> dielectrics are used as needed.<br />
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IBM is prototyping 22nm server parts right now, but even when they get into the servers for sale, I likely won't get my hands on one -- a bit beyond my procurement budget!<br />
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[1] S. Narasimha, <i>IEDM 2012</i> pp. 52-55<br />
[2] S. Iyer, <i>ASMC 2012</i><br />
[3] N. Butt, et al., <i>IEDM 2010</i> pp. 616-619<br />
[4] J.Bart et al, <i>IEEE Journal of Solid-State Circuit</i>, Jan 2011Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-86220509479643472772012-12-11T13:23:00.000-05:002012-12-11T15:19:24.455-05:00Intel details 22nm trigate SoC process at IEDMAfter launching their 22nm tri-gate high-performance logic product back in the spring, Intel have been promising to show off their SoC derivative, and yesterday was the day at the 2012 <a href="http://www.his.com/%7Eiedm" target="_blank">IEEE International Electron Devices Meeting</a>. [1]<br />
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As you can see from Table 1, we now have six transistor options; the high-voltage transistors use a thicker gate dielectric stack (<b>Fig. 1</b>), and the gate pitch and gate lengths have been tuned to suit the end purpose, and of course there is some (unspecified) source/drain engineering.<br />
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<i>Intel 22nm SoC transistor options</i> [1]</div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhDp_mBl0_uK0zHVEP6V3Y5lrS1wVVFlEqbL_QRfbbPkhXV8o5QBsXCn6yDrIYqYuwaGxvvPjSqypX-6kR6CwbleW9C2W-GxkiwAb8oyJBzpRc2Gke9SdqrKGFXj8hKnBZCbq4vUsyiJpp4/s1600/Fig+1.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="216" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhDp_mBl0_uK0zHVEP6V3Y5lrS1wVVFlEqbL_QRfbbPkhXV8o5QBsXCn6yDrIYqYuwaGxvvPjSqypX-6kR6CwbleW9C2W-GxkiwAb8oyJBzpRc2Gke9SdqrKGFXj8hKnBZCbq4vUsyiJpp4/s400/Fig+1.png" width="400" /></a></div>
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<i><b>Fig. 1:</b> TEM linear- and cross-sections of, and tilted SEM of, <br />logic (top) and high-voltage (bottom) transistors</i> [1]</div>
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If I read the paper correctly, the SoC process can incorporate up to twelve metal layers, with up to six 1× layers, and an extra 3× level, but only one 4× level <b>Fig. 2</b>). When it comes to the passives, the same MIMCAP layer is used as we saw in the CPU together with similar finger capacitors to the 32nm SoC; inductors are also formed in the 6μm thick top metal; and there are precision resistors available.<br />
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<i><b>Fig. 2:</b> Interconnect stacks for CPU (left) and SoC processes</i> [1]</div>
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A bunch of SRAM cells are offered, both six- and eight-transistor varieties, with the 6T cells ranging from the minimal 0.092 to 0.13 μm<sup>2</sup>. These show the quantization of the transistor size quite nicely -- if you look closely at <b>Fig. 3</b>, you can see that the number of fins used for each transistor increases with the size of cell, with the exception of the T3 and T4 PMOS pull-up devices, which only have one fin.<br />
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<i><b>Fig. 3:</b> Intel's 6T SRAM options in their SoC technology, including <br />high density / low leakage (HDC), low voltage (LVC), and high performance (HPC)</i> [1]</div>
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Overall Intel claims a 100-200 mV reduction in Vt for all transistor types, leading to a ~40% reduction in dynamic power.<br />
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Intel is trying to catch their SoC schedule up with the CPU launches, so we will likely see 22nm SoC chips next year, and the 14nm CPU and SOC processes should be launched in parallel, theoretically by the end of 2013.<br />
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[1] C-H Jan, <i>IEDM 2012</i> pp. 44-47
Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com1tag:blogger.com,1999:blog-5488132572864585098.post-23972986270474548392012-10-02T17:22:00.001-04:002012-10-02T22:31:38.996-04:00GLOBALFOUNDRIES takes on Intel with 14nm finFET “eXtreme Mobility” processA week after Intel were claiming that their 14nm process will be ready to go at the end of next year, GLOBALFOUNDRIES (GF) <a href="http://www.globalfoundries.com/newsroom/2012/20120920.aspx" target="_blank">announced</a> that they will have a 14nm finFET process for launch in 2014. Unfortunately they timed it to coincide with the iPhone 5, so we at Chipworks were tied up for a few days <a href="http://www.chipworks.com/blog/recentteardowns/2012/09/20/2467/" target="_blank">tearing it down</a>.<br />
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However, I don't want to ignore this development -- it could make the 2014 an interesting year! GF have dubbed the new process 14XM, for "eXtreme Mobility," since from the start it has been targeted on mobile applications -- after all, mobile products are the volume driver in the chip business these days.<br />
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And what's the biggest complaint from mobile users? Having to charge them so often, as battery technology has not improved at anything like a rate comparable to chip performance.<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgqld80txVSOuCws1VzNSDgmgaPgRbEpYgPSpN0tdHjXkkn0q6vwUdZMZ7S7_i8zUfQ8bjmAEpho8hYQICq8Yq5wowkhkSBPVmO2jifDMrRjXWW3fPbxZVxRX3N-dRh2sZfjWJ3tjLd85uG/s1600/Battery.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="320" mea="true" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgqld80txVSOuCws1VzNSDgmgaPgRbEpYgPSpN0tdHjXkkn0q6vwUdZMZ7S7_i8zUfQ8bjmAEpho8hYQICq8Yq5wowkhkSBPVmO2jifDMrRjXWW3fPbxZVxRX3N-dRh2sZfjWJ3tjLd85uG/s320/Battery.png" width="245" /></a></div>
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So while GloFo got started in high-<i>k</i> metal-gate (HKMG) making 32nm parts for AMD, they have seen the obvious and are generating low-power processes, beginning with the 28-SLP, moving to the 20-LPM, and now the 14XM.<br />
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The 20-LPM process claims a 40% reduction in power from the 28nm generation, and the 14XM claims 40%-60% increased battery life over 20-LPM. The 20nm generation is scheduled for next year, and as noted earlier 14XM is due out in 2014, a year later, breaking the two-year cadence that we've all got used to. Apparently 20nm wafers are running the full process in the Malta, NY fab right now.<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjI_d_4B0-Q-Fpj9ZwAhajnC6t8cOAZ1wPkDYyDAWlx-J0Lhkb2VsVrZYNzBa_lnc3FDqAzvVSOJEjB5CD5Hwv_ncHRF14xwXETyl4nwCp0klS0vogC-UmJvBfnqs5MIVVHsozxSbkWUjyU/s1600/GloFo+sl7.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="239" mea="true" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjI_d_4B0-Q-Fpj9ZwAhajnC6t8cOAZ1wPkDYyDAWlx-J0Lhkb2VsVrZYNzBa_lnc3FDqAzvVSOJEjB5CD5Hwv_ncHRF14xwXETyl4nwCp0klS0vogC-UmJvBfnqs5MIVVHsozxSbkWUjyU/s320/GloFo+sl7.png" width="320" /></a></div>
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They're accelerating the process launch by using the 20-LPM middle/back end-of-line metal stack with the finFET front end. In the 20nm process the 1x metal pitch is 64nm and the single-patterned metal is 80nm -- coincidentally, the latter is the same as Intel's tightest pitch in their 22nm product.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgFNzxdEkKAbBoLLYRvl9arqjgA4is88KFA1i0IIyuQrhDSf755SgGSX0SOj3MthBSpQu0PORzQ6upK-DwY5jHZyNmMjqctXAPLO7pk4fcIi1ZTmN6tgelx2W7SwXxfk3ts4JR70TVfipvW/s1600/CPTF2012+003_branded.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="202" mea="true" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgFNzxdEkKAbBoLLYRvl9arqjgA4is88KFA1i0IIyuQrhDSf755SgGSX0SOj3MthBSpQu0PORzQ6upK-DwY5jHZyNmMjqctXAPLO7pk4fcIi1ZTmN6tgelx2W7SwXxfk3ts4JR70TVfipvW/s320/CPTF2012+003_branded.JPG" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">20nm metal pitches shown at the 2012 Common Platform Tech Forum (CPFT)</td></tr>
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The use of the 3D finFET structure enables a higher performance/unit area, or lower power/unit area at a given performance at the transistor level. The graph below shows some estimates made by their R&D group.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj0cm-HbawBAUGvgmg9H6PJX-eYaMrL8wPQUUVMEyiKIYkJBkS1tWQeRrInAVh4RfRTmc3XGot72EXu0AXfCmoeP9u4rGVwUk4NseCLDlPhyxa_oqRTDUIJJu_2mJQOk2XPivfELVg2HXLJ/s1600/IEDM11.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="280" mea="true" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj0cm-HbawBAUGvgmg9H6PJX-eYaMrL8wPQUUVMEyiKIYkJBkS1tWQeRrInAVh4RfRTmc3XGot72EXu0AXfCmoeP9u4rGVwUk4NseCLDlPhyxa_oqRTDUIJJu_2mJQOk2XPivfELVg2HXLJ/s320/IEDM11.png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">SoC Performance vs. power -- lower power at constant frequency [1] </td></tr>
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Functional scaling itself will be limited to some extent by the 20-LPM metal density, but presumably some die shrink can be achieved by using more metal layers, and also the increased current density will allow some compaction since higher-current transistors will be smaller. Keeping single patterning will mitigate the cost, compared with double patterning for denser layers.<br />
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The process will also continue from the 20-LPM process in that it will use gate-last (replacement metal gate) technology on a bulk substrate. The R&D group in New York has published a couple of papers [2, 3] referencing a 40nm fin pitch, but 14XM will have a fin pitch of 48nm to leave some slack in the lithographic challenge, and minimize quantization errors. Together with the metal pitches of 64 and 80nm, it implies a 16nm grid as a basis for layout. The use of 64nm Metal 1 presumably also means that the contacted gate (CG) pitch will be 64nm.<br />
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The Intel 22nm process has a fin pitch of 60nm, and a CG pitch of 90nm, so it's not unreasonable to assume that their 14nm process will have similar numbers.<br />
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We will see whether the fin will be tapered similar to Intel's; these images (below) from CPTF seem to show a vertical fin atop the STI profile, but then, they are only schematics. Using a single (STI) etch to shape the fins (as I think Intel does) should certainly be less complex than trying to get vertical-walled fins on top of the STI trench sidewall.<br />
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The economic challenge in going to 14nm is almost as huge as the technical challenge, and keeping the cost/power/performance (CPP) metric in check as process complexity spirals upwards has caused inevitable concern. In particular, the cost benefits of shrinking die size tends to go away as the lithography demands double, triple, and even quadruple patterning.<br />
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Jen-Hsun Huang of Nvidia has publicized his concern about increasing wafer costs at last year's IPTC (International Trade Partner Conference) meeting -- the plot below shows the increasing gap in wafer cost between successive nodes:<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjuPPy3J_r9hEUA32QDh4hivyhjQshHytk8zRj3iLBFS8H_-ZAz_Ja9c_HPT9XbyhDYjZgIFxNmDF4PuvVwivLFFcIkW9LxHXsxo_yPipphdFwJWWB9ojMJeeD9Utxa7vcMMoALytLAYwJ4/s1600/Nvidia.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="240" mea="true" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjuPPy3J_r9hEUA32QDh4hivyhjQshHytk8zRj3iLBFS8H_-ZAz_Ja9c_HPT9XbyhDYjZgIFxNmDF4PuvVwivLFFcIkW9LxHXsxo_yPipphdFwJWWB9ojMJeeD9Utxa7vcMMoALytLAYwJ4/s320/Nvidia.png" width="320" /></a></div>
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So if GLOBALFOUNDRIES, or any other foundry, wants to keep the customers coming, they have to mitigate the cost increase going to the next node. Taking a hybrid approach such as the 14XM process should be an attractive option for their existing and future customers.<br />
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It's interesting to note that TSMC has changed tack slightly and are now saying that they will be using finFETs at 16nm, not 14nm. They are also claiming that their 20nm metal pitch is leading-edge at 64nm, although that's the same as GF's. It's tempting to wonder if TSMC will also use a hybrid approach and transfer their 20nm back-end to the 16nm node, since the arguments are the same. <a href="http://blogs.wsj.com/digits/2012/09/20/globalfoundries-moves-to-match-intels-transistors-and-timing/" target="_blank">Chenming Hu thinks so</a>, anyway. TSMC are predicting 16nm risk production in 2014.<br />
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We'll see if GF can match Intel's timing -- Mark Bohr sounded very confident at the Intel Developer Forum, when he said their 14nm product would be ready for the tail end of next year. Will we have GF-produced finFETs in early 2014? And will <a href="http://www.electroiq.com/blogs/chipworks_real_chips_blog/2012/03/glofo-s-finfets-are-better-than-intel-s-musings-from-cptf.html" target="_blank">their finFETs be better than Intel's</a>?<br />
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My thanks to Subi Kengeri for clearing up some of the technical details.<br />
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[1] A. Keshavarzi et al., Architecting Advanced Technologies for 14nm and Beyond with 3D FinFET Transistors for the Future SoC Applications, <i>Proc. IEDM 2012</i>, pp. 67-70.<br />
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[2] T. Yamashita et al., Sub-25nm FinFET with Advanced Fin Formation and Short Channel Effect Engineering, <i>Proc. VLSI 2011</i>, pp. 14-15.<br />
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[3] C.-H. Lin et al., Channel Doping Impact on FinFETs for 22nm and Beyond, <i>Proc. VLSI 2012</i>, pp. 15-16.Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com3tag:blogger.com,1999:blog-5488132572864585098.post-54413181389609312762012-07-10T10:35:00.001-04:002012-07-10T16:51:58.390-04:00The Elephant Has Left the Room – 450 mm is a Go!It's the day before Semicon opens up, and we have had a slew of announcements on 450 mm, the biggest of which was the joint <a href="http://www.asml.com/asml/show.do?lang=EN&ctx=5869&rid=46711" target="_blank">ASML</a>/<a href="http://www.intc.com/releaseDetail.cfm?ReleaseID=690165" target="_blank">Intel notice</a> that Intel will be taking a share of ASML as a way of funding 450 mm and EUV R&D. Simultaneously <a href="http://www2.imec.be/be_en/press/imec-news/imec450mm.html" target="_blank">imec released</a> that the Flemish government would invest in their upcoming 450-mm facility, and <a href="http://www2.imec.be/be_en/press/imec-news/450mm-capable-surfscan-sp3-systems.html" target="_blank">imec</a> and <a href="http://www.prnewswire.com/news-releases/kla-tencor-announces-installation-of-first-450mm-capable-surfscan-sp3-systems-161823515.html" target="_blank">KLA-Tencor</a> declared that a 450-mm capable SP3 450 unpatterned wafer defect inspection tool had been installed at imec.<br />
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ASML announced it as a “co-investment program” in which Intel would invest EUR829 million (about $1B) over the next five years, EUR553M of which would be in 450 mm R and D. Intel focused more on the R and D and described the financial details later.<br />
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</div><div class="separator" style="clear: both; text-align: center;"></div>They cited the classic economics of doubling the wafer size, and the potential die cost reduction:<br />
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All of which is logical, but ASML has been notably reticent about making any comments on 450-mm R and D in the past, to the point where some industry watchers (including me) have wondered if we would ever get there; if the biggest litho vendor isn’t on board, there won't be any 450-mm fabs even if all the other equipment companies are ready.<br />
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Which brings me to the elephant in the title. Last year at Semicon there was a 450 mm panel, and everyone was pontificating wisely, until Bob Johnson of Gartner commented on "the elephant in the room - ASML has no 450-mm program, so why are we bothering to even talk about it?" (my paraphrasing). Which kind of shut the whole thing down.<br />
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However, that particular pachyderm has clearly moved on, and we have an ASML roadmap with both 450 mm and EUV in it:<br />
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<div class="separator" style="clear: both; text-align: center;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi-1DVbqYFjhPJzCcwYV4jpchuNwy15rUvKNbpMWuyOIKCCuEhhUw4xJhM8FX1vThcZwmFiP8_LI923-9biuQ7wByvlrtUPyCwq9jwxdzoxSrLbKfasr8f07kmFLZS9oAFridSFXFghv-WF/s1600/New+Picture+%25282%2529.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img $ca="true" border="0" height="240" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi-1DVbqYFjhPJzCcwYV4jpchuNwy15rUvKNbpMWuyOIKCCuEhhUw4xJhM8FX1vThcZwmFiP8_LI923-9biuQ7wByvlrtUPyCwq9jwxdzoxSrLbKfasr8f07kmFLZS9oAFridSFXFghv-WF/s320/New+Picture+%25282%2529.jpg" width="320" /></a></div><br />
We won’t have any production tools until 2018, but at least a huge barrier to adoption is lifted; now there are just the simple engineering tasks of getting a substrate the size of a turkey platter exposed with patterns with feature sizes of 14nm or smaller. Has anyone said that this industry is crazy?<br />
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By coincidence Mike Splinter of Applied Materials was speaking at the <a href="http://www2.imec.be/be_en/education/conferences/itf2012-semi-us.html" target="_blank">imec Technology Forum</a>, and he commented that 300-mm had just about paid off its development costs as of now, roughly 14 years after the launch of the first systems. He guesstimated the costs for developing 450 mm as $15 - 20B, with an as yet unknown payoff time. (Has anyone said that this industry is crazy?) However, he also <a href="http://www.electroiq.com/blogs/chipworks_real_chips_blog/2011/07/a-semicon-west-snippet-amat-launches-new-products-prepares-for-450mm.html" target="_blank">said this time last year</a> that Applied would spend over $100M on 450 mm and that "450 mm is going to happen." <br />
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Clearly Intel has recognised that if it wants 450 mm to go forward, then it has to pony up some cash to encourage the litho side, and it is already invested in the consortium being set up at Albany. For anyone interested in the financial side of the deal, check out the press releases linked above, or watch ASML CFO <a href="http://asml.corptv.datiq.net/2012announcement/" target="_blank">Peter Wennink in a video</a>.<br />
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<div class="separator" style="clear: both; text-align: center;"></div>Looks like 450 mm is actually going to happen!Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-56229013826492194762012-07-06T10:34:00.000-04:002012-07-06T10:34:00.928-04:00Sony’s PS Vita Uses Chip-on-Chip SiP – 3D, but not 3DAt the tail end of last year Sony released their <a href="http://us.playstation.com/psvita/" target="_blank">PlayStation Vita</a>, and it was duly torn down by <a href="http://www.ifixit.com/Teardown/PlayStation-Vita-Teardown/7872/1" target="_blank">iFixit</a> and others. In due course we took it apart too, though we didn’t post it on our <a href="http://www.chipworks.com/en/technical-competitive-analysis/resources/recent-teardowns/" target="_blank">teardown blog</a>.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhJVBex8vbrSXF6lr0MN5CJ98ixO3SirkuGjsAA_tK4Jnz5_1QWnborZIpvZNFglVzDGTGcCKyCXHT5dICRoHm7EyHT82Lyd0ayMjSHAfIsiDL8XeWhPiNKolz2NSIEiULgzCDdWJF9VIL9/s1600/New+Picture+(6).png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="198" sca="true" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhJVBex8vbrSXF6lr0MN5CJ98ixO3SirkuGjsAA_tK4Jnz5_1QWnborZIpvZNFglVzDGTGcCKyCXHT5dICRoHm7EyHT82Lyd0ayMjSHAfIsiDL8XeWhPiNKolz2NSIEiULgzCDdWJF9VIL9/s320/New+Picture+(6).png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Sony CXD5315GG in the PlaySation Vita</td></tr>
</tbody></table>Inside we found the usual set of wireless chips, motion sensors, and memory, but the key to the increased performance of the PS Vita is the <a href="https://chipworks.secure.force.com/catalog/ProductDetails?sku=SON-CXD5315GG&viewState=DetailView&cartID=&g=&parentCategory=&navigationStr=CatalogSearchInc&searchText=sony" target="_blank">Sony CXD5315GG processor</a>, a quad-core ARM Cortex-A9 device with an embedded Imagination SGX543MP4+ quad-core GPU.<br />
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Above I said that we found memory, but actually the only discrete memory that we found on the motherboard was 4 GB of Toshiba flash; and Sony’s <a href="http://us.playstation.com/corporate/about/press-release/playstation-vita-expands-its-entertainment-experience.html" target="_blank">specification</a> states that there is 512 MB (4 Gb) regular RAM, plus 128 MB (1 Gb) VRAM (video RAM). In a phone that would tell me that there is memory in a package-on-package (PoP) configuration, mobile SDRAM in the top part and the processor in the bottom part.<br />
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However, when we took the part off the board and did a set of x-rays, the side view proved me wrong – it’s a stack, and the close-up shows that there appear to be five dies in there, a thick die at the base, a thinner one immediately on top and three smaller die on top of that. The second die down could be a spacer, since there don’t seem to bond wires going to it.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhzZ8noQpa1FnfjAeIAEvHEZcP_HncfKeUrEyIkKA32yCL2Z3gKvIbIl2YaT7-6yL4oG-vjnCVAHW-WFW0uurwyyWe91yHK2x7JQH5NyU_a0KcKetgC9uHA_aFSBYBaajMwhMB_JWTzvQ_P/s1600/New+Picture+%25281%2529.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="131" sca="true" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhzZ8noQpa1FnfjAeIAEvHEZcP_HncfKeUrEyIkKA32yCL2Z3gKvIbIl2YaT7-6yL4oG-vjnCVAHW-WFW0uurwyyWe91yHK2x7JQH5NyU_a0KcKetgC9uHA_aFSBYBaajMwhMB_JWTzvQ_P/s320/New+Picture+%25281%2529.png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Side x-ray images of Sony CXD5315GG</td></tr>
</tbody></table><div class="separator" style="clear: both; text-align: center;"></div></div>This immediately led us to speculate – if the second die up is the VRAM, is it wide I/O DRAM, and is it using through-silicon vias (TSVs)? Time for a real cross-section to check that out, and almost predictably we were disappointed:<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhnTCBOR0ngQW9sbVl0zy6TbI_AESlIdo2DupQ2lp8a7qASwPYYGGRlXws0wHyOZRSqKS9flabhgHbPj7Pa8Z4c01vGELGZRXnSD39Mcpr94__alSC2Xc2WCTZt1_3OewLbPVjqkfbl1h9x/s1600/New+Picture+%25282%2529.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="167" sca="true" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhnTCBOR0ngQW9sbVl0zy6TbI_AESlIdo2DupQ2lp8a7qASwPYYGGRlXws0wHyOZRSqKS9flabhgHbPj7Pa8Z4c01vGELGZRXnSD39Mcpr94__alSC2Xc2WCTZt1_3OewLbPVjqkfbl1h9x/s320/New+Picture+%25282%2529.png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Sony CXD5315GG package cross-sectioned</td></tr>
</tbody></table>This type of face-to-face connection showed up back in 2006 in the original Sony PSP, and Toshiba had dubbed it “semi-embedded DRAM”, now they are calling it “<a href="http://www.toshiba-components.com/ASIC/SiP.html" target="_blank">Stacked Chip SoC</a>”. The ball pitch is an impressive ~45 µm, almost as tight as<a href="http://www.electroiq.com/blogs/chipworks_real_chips_blog/2010/11/ti-ships-40-m-fine-pitch-copper-pillar-flip-chip-packages.html" target="_blank"> TI’s copper pillars</a>, but they are staggered to achieve 40-µm pitch.</div><br />
So what are the five chips that are in the stack? At the base we have the processor chip; face to face with it is a Samsung 1-Gb wide I/O SDRAM; and the top three dies comprise two Samsung 2-Gb mobile DDR2 SDRAMs, separated by a spacer die, and conventionally wire-bonded. The base die is ~250 µm thick, and the others ~100 – 120 µm.<br />
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When we look at the die photos of the processor and the 1-Gb memory, we can see that they are purposely laid out for the stacked-chip configuration, since in the centres of both is an array of matching bond pads.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgS3k8pMf37fa37c05KkeWHTfn7K1GgGfYMgH7V1sftFFjKtHuojHBv51jKyCSriD6QN43Eh1uew3s1bO0Jl7b6Ogg68jM1UBYM628B8VPiMcgIzh8qO4PwgT-ZoIqrCAN469gUbZlmRBbc/s1600/New+Picture+%25283%2529.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="190" sca="true" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgS3k8pMf37fa37c05KkeWHTfn7K1GgGfYMgH7V1sftFFjKtHuojHBv51jKyCSriD6QN43Eh1uew3s1bO0Jl7b6Ogg68jM1UBYM628B8VPiMcgIzh8qO4PwgT-ZoIqrCAN469gUbZlmRBbc/s320/New+Picture+%25283%2529.png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Die photos of the Sony CXD5315GG (left) and Samsung 1-Gb wide I/O SDRAM with bond pad arrays annotated</td></tr>
</tbody></table>Close examination reveals that there are 1080 pads in two blocks of 540 (2 sub-blocks of 45 rows of 6 pads), so likely 2 x 512 bit I/O operation, possibly sub-divided into 4 x 128.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgQ3QcwRyjpGr4QtyGEo7l7hov060Xk3Xqi9OTTAXSIeVhUDIfbR6sRo_0QFgFJox0lShJs55hkOHgEvwCQ8KD3HOjlWJhBLNPE4rxp0_qXbgUdK2c0zjdS_dXc2NRNZ-y6rzmDUqLUowcK/s1600/New+Picture+%25284%2529.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="278" sca="true" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgQ3QcwRyjpGr4QtyGEo7l7hov060Xk3Xqi9OTTAXSIeVhUDIfbR6sRo_0QFgFJox0lShJs55hkOHgEvwCQ8KD3HOjlWJhBLNPE4rxp0_qXbgUdK2c0zjdS_dXc2NRNZ-y6rzmDUqLUowcK/s320/New+Picture+%25284%2529.png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Wide I/O bond pad arrays in Sony CXD5315GG (top) and Samsung SDRAM</td></tr>
</tbody></table>Last year at ISSCC Samsung described a similar wide I/O DRAM using TSVs [1], claiming a data bandwidth of 12.8 Gb/s, four times the bandwidth of an equivalent LPDDR2 part. I doubt that the authors expected their design to be in a volume consumer device before the end of the year, but that seems to be what happened!<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh7XFjTEk-XOMdwdndIBu1LzytLJG_R1oUi9EvCPJaWe-smlEqvGs5YDenxJbnSnJOn3jRB6_tISFUT2WKh3PM7oKTdLLHE6QEnjVFAOb7WGBCmIMNmfutnznZB-kgPZ3OYg2H-gmuCEI4l/s1600/New+Picture+%25283%2529.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="195" sca="true" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh7XFjTEk-XOMdwdndIBu1LzytLJG_R1oUi9EvCPJaWe-smlEqvGs5YDenxJbnSnJOn3jRB6_tISFUT2WKh3PM7oKTdLLHE6QEnjVFAOb7WGBCmIMNmfutnznZB-kgPZ3OYg2H-gmuCEI4l/s320/New+Picture+%25283%2529.jpg" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Chip architecture of Samsung 1Gb Wide-I/O DRAM and SEM image of microbumps (Source: Samsung/ISSCC)</td></tr>
</tbody></table>This uses similar I/Os, but not the same as, the JEDEC wide I/O standard <a href="http://www.jedec.org/news/pressreleases/jedec-publishes-breakthrough-standard-wide-io-mobile-dram" target="_blank">issued earlier this year</a> (which calls for 50 rows of 6 pads in each block), and of course it predates it by about a year.<br />
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<div style="text-align: left;">By combining the processor with the different memories in the same package in the Vita, Sony and Toshiba have produced one of the few true system-in-package (SiP) parts that we have seen. And I would call it 3D, even though industry convention is now restricting that term to TSV-based parts – so it’s not 3D, in our current argot.</div><div style="text-align: left;"><br />
</div><div style="text-align: left;">In a way this device highlights the commercial barriers to introducing TSVs into the SiP world, since not only do the corresponding parts have to be designed to suit the I/Os, but at least for a two-stack the technology is already there; so the performance cost/benefit has to be critical enough to require TSVs for that third and more die. Admittedly the demands on mobile devices are increasing at an astounding pace, but it still seems a while before we’ll see TSVs in commercial devices. Time will tell!</div><div style="text-align: left;"><br />
</div>[1] J-S. Kim et al., A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4×128 I/Os Using TSV-Based Stacking, ISSCC 2011, pp. 496 – 498.Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com1tag:blogger.com,1999:blog-5488132572864585098.post-68785772674434498952012-04-24T12:39:00.000-04:002012-04-24T12:39:12.740-04:00Intel’s 22-nm Trigate Transistors Exposed<div class="separator" style="clear: both; text-align: center;">
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Last week Intel had their Q1 conference call for financial analysts, and revealed that the 22-nm Ivy Bridge parts would make up 25% of their shipment volume in the second quarter of this year. That means that a good quantity will already will have shipped, and we managed to track some down in Hong Kong a few weeks ago. Of course we got in touch ASAP and the parts duly arrived, and they were the real thing.<br />
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Fig. 1 Intel Xeon E3-1230V2 Server CPU </div>
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<br />We obtained samples of Xeon E3-1230 v2 CPUs, which are four-core, 3.3 GHz, 64-bit parts intended for the server market. Here is a die photo of the transistor level, with annotations from <a href="http://newsroom.intel.com/docs/DOC-2735" target="_blank">Intel's Ivy Bridge launch</a> yesterday:<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiDM_h0keCTjUUrsOJYvD9uMcQ69HKaCZQeM2bpTb1UAY_2OkfWVbQj3s4eWSBkqPAQeBDaeODC1LDPz5wKez1ruBMqaLK3jgU-Ts9FYUbMhyHibXlrKl3HgpTZ4M3QXdIQkMyQwzVOSDxR/s1600/E3-1230V2_die_backside_poly_118538_adj_r_branded-ann.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="133" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiDM_h0keCTjUUrsOJYvD9uMcQ69HKaCZQeM2bpTb1UAY_2OkfWVbQj3s4eWSBkqPAQeBDaeODC1LDPz5wKez1ruBMqaLK3jgU-Ts9FYUbMhyHibXlrKl3HgpTZ4M3QXdIQkMyQwzVOSDxR/s320/E3-1230V2_die_backside_poly_118538_adj_r_branded-ann.png" width="320" /></a></td></tr>
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Fig.2 Intel Xeon E3-1230V2 Die </div>
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A quick cross-section reveals that Intel have stayed with the nine metal layers used in the last two generations:<br />
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Fig. 3 Intel Xeon E3-130V2 General Structure</div>
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A closer TEM image (Fig. 4) shows the lower metal stack and a pair of multi-fin NMOS and PMOS transistors. This section is parallel to the gate, across the fins, and we can see the contact trenches and metal levels M1 up to M5.<br />
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We have to digress here a little to explain what we’re looking at. A typical TEM sample is 80 – 100 nm thick, to be thin enough to be transparent to the electron beam and at the same time have enough physical rigidity so that it does not bend or fall apart. <br />
<br />Here we are trying to image structures in a die with a gate length of less than 30 nm; so if we make a sample parallel to the gate, and if the sample is aligned perfectly along the centre of the gate, then it will contain the gate plus at least part of the source/drain (S/D) silicon and contacts on either side.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEibid6UxAIWmyGWXiLeQhXu7hR41-Zko0O2ssOM646LAFnWtgi6S7mj_U91Ahp67uqtFMKVWRBB28ptRB4avq9sYnciF4vwVx-_ZZmRQ4tjnL9D7JgCWxocVpY1WiIvrSjnkgQnRSwmBilh/s1600/Lower+metals+%2526+transistors.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="268" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEibid6UxAIWmyGWXiLeQhXu7hR41-Zko0O2ssOM646LAFnWtgi6S7mj_U91Ahp67uqtFMKVWRBB28ptRB4avq9sYnciF4vwVx-_ZZmRQ4tjnL9D7JgCWxocVpY1WiIvrSjnkgQnRSwmBilh/s320/Lower+metals+%2526+transistors.png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><div class="wp-caption-text">
Fig. 4 TEM Image of Lower Metals and NMOS and PMOS
(right) Transistors</div>
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That is what we see above – I have labeled the gate and contact stripes, and we have PMOS on the right and NMOS on the left. The tungsten-filled contacts obscure parts of the gate, but we can clearly see that the PMOS S/D fins have epitaxial growth on them, and the fins have an unexpected slope – a little different from Intel’s tri-gate schematic shown last year –see Fig.5.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg9S1a0C97digSRgFdICxPZqMhdBGrxI-A9_77MTep9n9FOe72dl5y_-KWDgSQ3GdKzE5_plypN5sTx3MF6aqh-NbCGfrRW30rdQ8RV3VA2iENSt4FWanTkIFATrQBIw-RtLiiqFTKEkuB2/s1600/Intel+trigate.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg9S1a0C97digSRgFdICxPZqMhdBGrxI-A9_77MTep9n9FOe72dl5y_-KWDgSQ3GdKzE5_plypN5sTx3MF6aqh-NbCGfrRW30rdQ8RV3VA2iENSt4FWanTkIFATrQBIw-RtLiiqFTKEkuB2/s320/Intel+trigate.png" width="317" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><div class="wp-caption-text">
Fig. 5 Intel Schematic of Tri-Gate Transistor</div>
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If we zoom in a bit further into the PMOS gate (Fig. 6), we can see how the gate wraps over the fin, and the rounded top of the fin. The thin dark line adjacent to the fin is the high-k layer and just above that is a mottled TiN layer that is likely the PMOS work-function material, as in the 32-nm and 45-nm parts.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgN9BCp8NPsIxJUO2Yxkv41eIR27d5TQ5Q5nWFpigRzC0qxXDwKGU7VGsXVHxNPvnesE4MkfZmV4VEoZIoZZx8n07aKYa2gWF8KHWXQ5evg25asLh3OJhgdPx2uRDda8LEFA2s7yyd057HA/s1600/GATE+OVER+FIN+64K-r-c_branded.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="298" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgN9BCp8NPsIxJUO2Yxkv41eIR27d5TQ5Q5nWFpigRzC0qxXDwKGU7VGsXVHxNPvnesE4MkfZmV4VEoZIoZZx8n07aKYa2gWF8KHWXQ5evg25asLh3OJhgdPx2uRDda8LEFA2s7yyd057HA/s320/GATE+OVER+FIN+64K-r-c_branded.png" width="320" /></a></td></tr>
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Fig. 6 TEM Image of PMOS Gate and Fin Structure</div>
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Fig. 7 shows a section of an NMOS transistor. There is a ‘ghost’ of the contact behind the gate, but the gate structure itself looks similar to the PMOS, with the exception of the work-function material just above the high-k layer (as expected).<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEglJQ0e6PBKFtSFjwVI4M3sJH-yZ1yD8GbjBHDp1s26rRj7iPFdo1NXMWOGWe_LXro1kLhMPxFxZRYmJ7vYoguJyY1YBQMKNJVispeGUFQODRBhscDAh4wN9vqjPOn3oOq1ucsWATAHS5N3/s1600/fins_under_gate%2526cont_64K_ann-r-c_branded.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="287" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEglJQ0e6PBKFtSFjwVI4M3sJH-yZ1yD8GbjBHDp1s26rRj7iPFdo1NXMWOGWe_LXro1kLhMPxFxZRYmJ7vYoguJyY1YBQMKNJVispeGUFQODRBhscDAh4wN9vqjPOn3oOq1ucsWATAHS5N3/s320/fins_under_gate%2526cont_64K_ann-r-c_branded.png" width="320" /></a></td></tr>
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Fig. 7 TEM Image of NMOS Gate and Fin Structure</div>
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Fig. 8 gives me an opportunity to show off our new TEM – we have recently purchased an FEI Osiris machine, which upgrades our capability considerably. Here we have a lattice image of a fin in an NMOS transistor; the diamond-like layout of the pattern of dots is actually created by the columns of atoms in the silicon crystal lattice. This tells us that the sample is oriented in the <110> direction, which given that silicon has a face-centred cubic structure in which equivalent planes are at right angles, means that the channel direction is also <110>.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgkPaQNZsy_SzV6AKOae5qOlCFhuiLUe7a0ZgpA0L4NWIQbr62APIA6ifCgXLwwpPBgkN94mtsqdC15rBRazw-Rt7klSUHgdT2AoAtpSRzjh6mGvJrS60GiOQlPccvA5QgjZp4g4Y4-Oena/s1600/FIN+410K+-c_branded.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgkPaQNZsy_SzV6AKOae5qOlCFhuiLUe7a0ZgpA0L4NWIQbr62APIA6ifCgXLwwpPBgkN94mtsqdC15rBRazw-Rt7klSUHgdT2AoAtpSRzjh6mGvJrS60GiOQlPccvA5QgjZp4g4Y4-Oena/s320/FIN+410K+-c_branded.png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><div class="wp-caption-text">
Fig. 8 TEM Lattice Image of NMOS Fin Structure</div>
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To fully understand what we’re looking at, of course, we need to see what’s happening in the orthogonal direction, along the fin and cross-sectioning the gate – as in Fig. 9. This shows an array of PMOS transistors over a single fin, four functional gates and two dummy gates at the ends of the fin. Again the TEM sample is thick compared with the feature size, so we are seeing the gate on the side(s) of the fin, not just the top. The fin ends have the same taper as in Figs 6 and 7.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjyauMmdVo44ZOWJrKC0SI-HD_zlnecVVsCQ4AdoISIl2UnnOt9Y1kO_vyOSpx0a4LHjoZL5kjv_9OL6_7EfpusgPsRxGvaKUV38VPU4L6P7wHvVrY5x-IkwTJCORw8wuAC_I1PzDNhvJIp/s1600/M1_M0_CG_pitch_18K_ann-r-c_branded-c_branded.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="261" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjyauMmdVo44ZOWJrKC0SI-HD_zlnecVVsCQ4AdoISIl2UnnOt9Y1kO_vyOSpx0a4LHjoZL5kjv_9OL6_7EfpusgPsRxGvaKUV38VPU4L6P7wHvVrY5x-IkwTJCORw8wuAC_I1PzDNhvJIp/s320/M1_M0_CG_pitch_18K_ann-r-c_branded-c_branded.png" width="320" /></a></td></tr>
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Fig. 9 TEM Image of PMOS Transistors</div>
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As announced by Intel, there is embedded SiGe in the source/drains, although not etched to the <111> planes as in the 32- and 45-nm product. It also looks as though the tops of the gates have been etched back and back-filled with dielectric, and the contacts are self-aligned as in memory chips.<br />
<br />Zooming in on the PMOS transistor in Fig.10, the image is a bit fuzzy, but the SiGe is clearly in a rounded cavity with no facets on the top, though there are facets on the sides of the fin (see fig. 4).<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhLBFHiDEKMdhMsGKqZJQJLmZnz6JuBfkbYpYsSaoI-NAu0oYL5nb_BI3GSkK-gClWIXOwURUE-uRCXsMK_pxrC-R_mG7KbrViEZvr4cV8zOn9w-bGxMfohlE0CGYrZB710MlEtJzDnff7a/s1600/PMOS+lge.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhLBFHiDEKMdhMsGKqZJQJLmZnz6JuBfkbYpYsSaoI-NAu0oYL5nb_BI3GSkK-gClWIXOwURUE-uRCXsMK_pxrC-R_mG7KbrViEZvr4cV8zOn9w-bGxMfohlE0CGYrZB710MlEtJzDnff7a/s320/PMOS+lge.png" width="296" /></a></td></tr>
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Fig. 10 TEM Image of PMOS Transistor</div>
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Looking at the NMOS equivalent (Figs. 11 and 12), we see a similar structure – there seems to be an epitaxial interface, and the silicide(?) seems to protrude slightly above the fin.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEinBaw8lPKgFO9fy2-TNd-z6Y1HdQeKUhXlPJHZHS6DfiL2jrNLfB9pE8g966iFcDYZCwQFI-RjP_ojMF06DNDc_FJE0AOgKEua4-powtGrk9_wy7TSPX84rf5L27pR8sTOJxJZl0hMkizj/s1600/NMOS+GATES+%2526+CONT+27K-r-c-a_branded.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="168" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEinBaw8lPKgFO9fy2-TNd-z6Y1HdQeKUhXlPJHZHS6DfiL2jrNLfB9pE8g966iFcDYZCwQFI-RjP_ojMF06DNDc_FJE0AOgKEua4-powtGrk9_wy7TSPX84rf5L27pR8sTOJxJZl0hMkizj/s320/NMOS+GATES+%2526+CONT+27K-r-c-a_branded.png" width="320" /></a></td></tr>
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Fig. 11 TEM Image of NMOS Transistors</div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhLvONwQWYlUV6LOg37qEVPVLIDj4eDGenTIaZx1EFtpT5eL9mJAeYIN8kJwNeWJ6UUsoVq6aqAsOYy6XFpFULn7HDRz_OWlgt8qnu1yBD6eUgD9GqIO3N-_GaZMwLMFEVuDjjZddWiBcmW/s1600/NMOS+lge.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="304" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhLvONwQWYlUV6LOg37qEVPVLIDj4eDGenTIaZx1EFtpT5eL9mJAeYIN8kJwNeWJ6UUsoVq6aqAsOYy6XFpFULn7HDRz_OWlgt8qnu1yBD6eUgD9GqIO3N-_GaZMwLMFEVuDjjZddWiBcmW/s320/NMOS+lge.png" width="320" /></a></td></tr>
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Fig. 12 TEM Image of NMOS Transistors</div>
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It is hard to say much about the gates here, either NMOS or PMOS, because of the sample thickness problem; we are viewing a slice that includes the gate on both sides of the fin and the fin itself. Fortunately we have images of gate metal over STI and they are less confusing. <br />
<br />Figure 13 is a composite image of NMOS and PMOS gates so that the differences are highlighted. The dark line surrounding the gate structures is the Hf-based high-k, and within that are the two work-function materials, likely TiN for PMOS and TiAlN for NMOS. (The columnar structure of the PMOS TiN is visible in the right half of the image.)<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgjZwiDiRDRa4v0Mk2xEwihXQ-B1aNcsM5b2JTTwx8iRgTzxDd_RgJSvhhpgR1WIC20H99bjB6ogiFnz-ifJwc3DOR_-y8yCi4XKEubu-YbZtznY3SQIDrd6nc4Yl1iPw_moEQvk9eHY-Ap/s1600/Composite-c_branded.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgjZwiDiRDRa4v0Mk2xEwihXQ-B1aNcsM5b2JTTwx8iRgTzxDd_RgJSvhhpgR1WIC20H99bjB6ogiFnz-ifJwc3DOR_-y8yCi4XKEubu-YbZtznY3SQIDrd6nc4Yl1iPw_moEQvk9eHY-Ap/s320/Composite-c_branded.png" width="251" /></a></td></tr>
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Fig. 13 Composite TEM Image of NMOS/PMOS Gates </div>
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The fill has been changed from TiAl in the earlier parts to tungsten. It is more prominent in the NMOS gates than the PMOS, because the PMOS structure includes both work-function metals, whereas the TiN has been etched out of the NMOS gates. At the 45-nm node Intel used tensile tungsten in the contacts to apply channel stress – have they transposed this to the gates in the 22-nm process?<br />
<br />Just to finish up, so that this is still a blog, not a paper (I don’t want to go on too long) – fig. 14 shows a sample delayered to expose the transistors, and imaged on a tilt angle. Both the gates and the fins show up nicely, and we can actually see tiny spikes of SiGe in the PMOS source/drains. The small pillars in between the fins in the NMOS areas are residual bits of contact metal. I think it’s a cool image!<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEimYNEMyGJjWa6-R89YvAZ9YtlcqTj4O2PlagF8Q8_HtTTxAi6vOpl7fCl5fRmHEyFsVTW2p9BTWcQU1Vk8rdu3HjXAwxg_4fGItOsq5tu1nrVYj0881kAbOkrvCL2YXRr0Ws6r-D430cLp/s1600/SEM+tilt.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="238" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEimYNEMyGJjWa6-R89YvAZ9YtlcqTj4O2PlagF8Q8_HtTTxAi6vOpl7fCl5fRmHEyFsVTW2p9BTWcQU1Vk8rdu3HjXAwxg_4fGItOsq5tu1nrVYj0881kAbOkrvCL2YXRr0Ws6r-D430cLp/s320/SEM+tilt.png" width="320" /></a></td></tr>
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Fig. 14 Tilt SEM Image of NMOS/PMOS Transistors </div>
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We are just getting into the full scope of the<a href="https://chipworks.secure.force.com/catalog/ProductDetails?sku=INT-E3-1230V2&viewState=DetailView&cartID=&g=&parentCategory=&navigationStr=CatalogSearchInc&searchText=Intel" target="_blank"> analysis</a>, so likely more to come in the next few weeks!<br />
I'm still tweeting as @ChipworksDick, for those that way inclined..Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0tag:blogger.com,1999:blog-5488132572864585098.post-42033401925536299582012-04-12T13:21:00.000-04:002012-04-12T13:21:25.605-04:00Intel to Present on 22-nm Tri-gate Technology at VLSI SymposiumJust published is the press release and tip-sheet on the 2012 VLSI Symposia on VLSI Technology and Circuits, this year in Hawaii. Listed first in the VLSI Technology highlight papers is Intel’s paper, “<em>A 22nm High-Performance and Low-Power CMOS Technology Featuring Fully Depleted Tri-Gate Transistors, Self-Aligned Contacts and High-Density MIM Capacitors</em>”, to be presented by Chris Auth in slot T15-2.<br />
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There was a fair bit of frustration at last year’s IEDM that there was no Intel paper on their tri-gate technology, although they had several others at the conference. The Intel folks I talked to said that there was reluctance to publish, since the other leading-edge semiconductor companies were not presenting – conferences were no longer the exchange of information that they have been in the past. I have to say I agree, some companies are keeping their technological cards very close to their corporate chests these days!<br />
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Also, no product was in the public domain at that point, though Intel claimed to be in production. By the time VLSI comes around in June, we should all be able to get Ivy Bridge based Ultrabooks, and we at Chipworks will have pulled a few chips apart.<br />
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In the paper the process is claimed to have “feature sizes as small as eight nm, third-generation high-k/metal gate stack technology, and the latest strained-silicon techniques. It achieves the highest drive currents yet reported for NMOS and PMOS devices in volume manufacturing for given off-currents and voltage. To demonstrate the technology’s versatility and performance, Intel researchers used it to build a 380-Mb SRAM memory using three different cell designs: a high-density 0.092- µm2 cell, a low-voltage 0.108- µm2 cell, and a high-performance 0.130-µm2 cell. The SRAM operated at 4.6 GHz at 1 V.”<br />
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The tip-sheet also posted the first Intel tri-gate images that I’ve seen in a while:<br />
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<tr><td class="tr-caption" style="text-align: center;">TEM images of Intel 22-nm PMOS tri-gate transistor (a) and source/drain region (b) <br />
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</tbody></table>Here we are looking at sections parallel to the gate, across the fin. There is no scale bar, so fin width is an unknown; and the taper on the fin is a bit of a surprise. The top of the fin is rounded, likely to avoid reliability problems from electric field concentration at corners.<br />
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In the gate metal, there seems to be a layer of titanium nitride (TiN) above the thin dark line that is the high-k, so we can surmise that the PMOS work-function metal is TiN, as in previous generations. The gate fill itself is very black, so that appears to have been changed from the Al/Ti fill used before; possibly to tungsten or some other heavier metal.<br />
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The source/drain image confirms the use of epi, and the darker area is again likely SiGe, both for strain and resistance improvement. At the moment it’s hard to say if the taper is a function of manufacturing convenience (easier to etch?), or if there are some device physics advantages that improve transistor operation. We’ll see in June!Dick Jameshttp://www.blogger.com/profile/07494545281580747788noreply@blogger.com0