Entitled "3D Copper TSV Integration, Testing and Reliability," they described a node-agnostic through-silicon via (TSV) technology which takes a via-middle configuration, making contact to the upper metal (fat-wire) layers in the device structure. By "node-agnostic" they mean that they proved the concept in devices fabbed on processes ranging from 90nm down to the 32nm HKMG process. In doing so, the TSVs have anything from three to nine metal layers below the contact level, and have to cope with dielectric k-values from 4.1 down to 2.4, and bulk and SOI wafers.
The paper doesn't specifically say so, but it appears that the TSVs are annular. Once the lower metal/dielectric stack is formed (including the via dielectric for the metal layer that contacts the TSVs), the TSVs are drilled through to the silicon, and then a Bosch etch is used to drill the vias about 100μm into the substrate, with a minimum pitch of 50μm.
After drilling, a conformal oxide is deposited, the barrier and seed layers are sputtered in, the copper fill is plated in, and any excess copper is CMP'd off. The dielectric for the contact level metal is put down, and then the top fat-wire metal levels are conventionally defined.
Fig.1: SEM cross-section image of annular TSV integrated into M10 level in 45nm technology.
Fig. 1 above shows the TSV contacting the metal 10 level in a 12-metal part. If we guesstimate that M10 is ~1μm thick, that gives us a TSV diameter of about 15μm (which agrees with a verbal comment at the presentation), and the annular copper ring is 4-5μm thick.
Fig.2: Cross-section of TSV bottom, showing Bosch-etch striations and fully-filled via.
It appears by the time M3 is complete, there's about 250μm of bow in the wafer, which continues and will likely get worse by the end of wafer fab. That makes it difficult to bond the wafer flat for thinning, so at the via-2 and via-3 levels compressive oxide is used which pulls the wafer flat again -- see Fig. 3 below.
Fig.3: Wafer bow vs. metal step and change with high-stress oxide at via-2 and via-3 levels.
That will mean that if TSVs are to be used there will have to be a discrete process module within the BEOL, and also the M2/M3 levels will have to be laid out to compensate for dense oxide rather than low-k in processes at 90nm nodes and below. Another cost adder for TSVs!
The completed wafers were bonded to glass handle wafers and thinned to expose the copper at the bottom of the TSVs, after which a protective oxide/nitride was deposited and patterned before forming and defining a copper redistribution layer (RDL). Lead-free C4 solder balls were then put on the the RDL, and the thinned TSV wafer was ready for joining to another die or substrate. After dicing the dies can be bonded with the RDL side on a package substrate with the device side face-to-face with another die, or face down with another die flip-chipped on to the RDL.
Fig. 4 shows a module in which a thin TSV wafer has been packaged RDL-down and another full-thickness die face-to-face with the thinned die.
Fig.4: Module containing thinned TSV die stacked face-to-face with full thickness die.
Test devices were subjected to considerable thermal and reliability testing without adverse effects. The TSV etch process was shown to affect nearby PFETs under certain conditions, but was optimized to solve the problem. The stress associated with the vias was not significant and not expected to create any mobility effects in nearby transistors.
As another test of the TSV process, a 32nm SOI 3D embedded memory module was fabricated with a 128Mb DRAM stacked on top of a 96Mb general purpose DRAM; both with 0.039m2 eDRAM cells in high-k/metal gate technology. The memories were tested with no performance or retention degradations observed.
I've no idea when we'll see a real memory cube in production; no dates were given in the announcement, but hopefully sometime next year. Whether we'll be able to get hold of one is another matter!
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