Samsung’s 3x DDR3 SDRAM – 4F2 or 6F2? You Be the Judge..

We recently acquired Samsung’s latest DDR3 SDRAM, allegedly a 3x-nm part. When we did a little research, we found that the package markings K4B2G0846D-HCH9 lined up with a press release from Samsung last year about their 2 Gb 3x-nm generation DRAMs. My colleague at Chipworks, Randy Torrance, popped the lid to take a look, and drafted the following discussion (which, amongst other things, raises the perennial question for us reverse engineers - how do you define a process node in real terms?). Now read on..

The first thing we did was measure the die size. This chip is 35 sq mm, compared to the previous generation 48-nm Samsung 1Gb DDR3 SDRAM, which is 28.6 sq mm. Clearly this 2 Gb die is much smaller than 2X the 48-nm 1 Gb die, so our assumption that we have a 3x nm part looks good so far.

Die Photo of Samsung 3x DDR3 SDRAM

Next we did a bevel-section of the part to take a look at the cell array. We were surprised with what we found. The capacitors are laid out in a square array instead of the more usual hexagonal pattern (see below), and the wordline (WL) and bitline (BL) pitches are both about 96 nm. The usual method of determining DRAM node is to take half the minimum WL or BL pitch. That places this DRAM at the 48-nm process node, the same as the previous Samsung generation of 48 nm. So why does the die size look like it should be a smaller technology? For this we need to look at cell size.

Plan-View TEM image of Capacitors in Samsung 3x-nm SDRAM

But before we get into that we should discuss the DRAM convention of describing the memory cell size in terms of the minimum feature size, F. Historically, DRAM cells have used an 8F² architecture for many years. This allows for the use of a folded bitline architecture, which helps reduce noise. In order to decrease cell area, companies came out with the first 6F² cells in 2007; this 6F² architecture is now used by all major players in the DRAM market. The guys at ICInsights published the plot below in the latest McLean report which nicely illustrates the progress:


DRAM Cell Size Reduction Through the Years

The 48 nm SDRAM has a cell size of ~0.014 sq µm. This new SDRAM has a cell size of 0.0092 sq µm. Clearly this cell is much smaller than the 48 nm generation. If we take the half-WL pitch as the minimum feature size (F), we get an F of 48 nm for this process. The cell area of 0.0092 sq µm is exactly 4 x F, squared, 4F². Is this the world’s first 4F² cell? From this point of view it certainly appears so. The cell is four times the size of the minimum feature, squared. But, there are other ways of looking at this.

A 4F² architecture is defined as having a memory cell at each and every possible location, that being each and every crossing of WL and BL, with the cell being 2F x 2F. This is in fact what we see on this Samsung DRAM, so maybe we are looking at the first 4F² architecture. But let’s look just a bit closer to be sure.

We compared the poly and active layout under the array between the 48 nm SDRAM and this new one. The images are shown below. As can be seen, both have very similar layouts. The angle of the active silicon (diffusion) direction is about the same. The active areas are ovals. Each diffusion has two wordlines crossing it. There is a gap between all the active areas, such that a third WL does not cross active on this diagonal active direction.

Samsung K4B1G0846F 48nm 1 Gb DDR3 SDRAM,
Poly and Active Area Image under Cell Array

Samsung K4B2G0846D 2Gb DDR3 SDRAM,
Poly Remnants and Active Areas under Cell Array

This new DRAM clearly has a very similar cell layout to the previous one. In both cases the wordlines do not have a transistor under them at every possible location that a transistor would fit. Rather, one of every three possible transistor locations is filled with a break in the diffusion stripe. This is really a better definition of a 6F² cell, since in a 6F² architecture 2/3 of the WL/BL intersections are filled with storage cells. As we noted above, a 4F² cell really should have transistors at every possible transistor location.



When we look at the pitch of the diffusions in this new DRAM, we see it is much tighter. In fact, along the WL direction the diffusion pitch is now 64 nm, whereas in the 48 nm SDRAM this pitch was 96 nm. So if you take half the minimum pitch in the chip as the node, this is a 32-nm part (ITRS 2009 still defines F as half the contacted M1 pitch, which would be 48 nm).

So, do we have a 32 nm node, and a 6F² architecture? Maybe. The only issue is that if we use 32 nm as F, then when we plug that into the 6F² equation we get 0.0061 um² as the cell size. However, the cell size is actually 0.0092 um². If we use that number and use the equation to calculate F we find that F=39nm. So… do we call this a 32 nm or a 39 nm node? It depends how you calculate it - either way it's a 3x!

So, although it’s a little disappointing that I don’t think we can announce the worlds first 4F² DRAM, we can announce the worlds smallest node, 32 or 39 nm, production 6F² DRAM.

Samsung have had to put in a few process tweaks to squeeze the cells into the much smaller area, mostly at the transistor and STI level. We’re still looking at it, so we may not have the whole story yet, but some of what we’ve seen so far is:

• Ti-? (likely TiN)-gate buried wordline transistors

• STI filled with nitride in the array

• Bitlines at the same level as peripheral transistors

Our up-coming reports will give many more details on this fascinating part.

Common Platform Goes Gate-Last – at Last!

At the IBM/GLOBALFOUNDRIES/Samsung Common Platform Technology Forum on Tuesday, Gary Patton of IBM announced that the Platform would be moving to a gate-last high-k, metal-gate (HKMG) technology at the 20-nm node.

At the 45- and 32-nm nodes there has been a dichotomy between gate-last as embodied by Intel, TSMC, and UMC, and gate-first, promoted by the Common Platform and others such as Panasonic. (Though, to be realistic, Intel’s is the only HKMG we’ve seen so far, and the only 32-nm product.)

The split puzzled me a bit, at least for high-performance processes, since Intel have clearly shown that for PMOS, compressive stress using embedded SiGe source/drains is a really big crank that is enhanced by removal of the dummy polysilicon gate in the gate-last sequence. In fact, in their 32-nm paper at IEDM 2009 [1], the PMOS linear drive current exceeds NMOS, and the saturated drive current (Idsat) is 85% of NMOS. This trend is shown below:



Intel Drive Currents at the Different Nodes [1]

 We can clearly see the narrowing between NMOS and PMOS drive currents at the 45-nm node, namely with the start of replacement gate (gate-last) technology.

So it seems obvious that to have high-performance PMOS, gate-last is the way to go; admittedly IBM and their allies have been using compressive nitride for PMOS, which Intel never have (at least to my knowledge), but there are limitations to that – now that contacted gate pitch has shrunk to less than 200 nm, there is not much room to get the nitride close to the channel - a problem that will increase with further shrinks.

So in a way it’s not surprising that the Platform has made the change; nitride stress is running out of steam, and gate replacement offers improved compressive stress for PMOS, and other stress techniques for NMOS (Intel builds some stress in with the gate metal).

Gary Patton said that IBM have been evaluating gate-last in parallel with gate-first since 2001, and it’s logical that they and their partners should. Both GLOBALFOUNDRIES and Samsung have published on gate-last, so there has been some evidence of checking out the parallel paths.


GLOBALFOUNDRIES PMOS and NMOS (right) Gate-Last Transistors [2]

 

Samsung Gate-Last Transistor [3]

Patton said that they selected gate-first in 2004; judging by their papers, Intel took their decision in 2003. The rationale that he put forward for the change to gate-last involved four points:

• Density – gate-first has higher density, since gate-last requires restricted design rules (RDRs). That prevents orthogonal layout, requiring local interconnect; but at 20-nm RDRs are needed for lithography, so that advantage disappears.
• Scaling – it’s easier to scale without having to cope with RDRs; at 20-nm there’s no choice.
• Process simplicity – it’s obviously easier to shrink if you can keep the same process architecture, whether it be to 32- or 20-nm
• Power/performance – the gate last structure allows strain closer to the channel, increasing performance; but fully contacted source/drains increase parasitic capacitance, slowing things down. According to Patton these net each other out for a high-performance process, making the gate first/last decision neutral. For low-power processes, strain is not used at the 45/32-nm nodes, so gate-first gives better power/performance metrics.  At 20-nm strain has to be used for low-power, and with the need for RDRs and local interconnect, the balance shifts in favour of gate-last.

So it appears that for the Platform the equation between pure transistor performance, process convenience, and power/performance made gate-first the choice at 45/32/28-nm, but at 20-nm the balance changes to make gate-last the way to go. That was likely influenced by the adoption of immersion lithography between 65- and 45-nm, which reduced the need for RDRs.

Intel presumably did similar sums during their 45-nm development, and figured that using RDRs would save them the cost of going to wet lithography at that node, and at the same time adopting gate-last technology would give them a manufacturing advantage. (My speculation is that they had also concluded that their version of gate-last may be more complicated to start up, but would prove to be more manufacturable than struggling with the instabilities that seem to go with the gate-first work-function materials. I guess they’ve proved that!)

Interestingly, now that Intel is using immersion lithography at 32-nm, they have loosened up on the RDRs, there’s more flexibility in the layout than there appeared to be at 45-nm.

I have to congratulate the Common Platform marketing guys on putting up a live webstream of the Technology Forum – I couldn’t get to the event itself, so wouldn’t have been able to comment without it. The stream will be available until April 29, so if you want to see Gary Patton for yourself, you can.



Screen Shot of Gary Patton of IBM at the Common Platform Technology Forum

Unfortunately, talking to my journalist colleagues, no slide sets were available, even at the press conference, so watching the stream occasionally leaves you puzzled as to what’s being talked about; and as you can see from the screen shot above, the room screens were carefully blanked out for the camera. Also, the breakout sessions in the afternoon were not streamed, or if they were, not recorded for later viewing. Still, kudos to the Platform for the live stream we did have, and the pre-recorded panel sessions!

From Gary’s and other comments at the Forum, it’s clear that the first HKMG products will be launched at 32-nm, and 28-nm will be following along fairly soon after. We can’t wait to see some!

For those waiting for more details if last year’s IEDM, I will finish my review; there were 36 sessions with 212 papers, so not a small task to do conscientiously, the Christmas break interrupted things, and there have been distractions since (like the Forum!), but I will get there!

References:

1. P. Packan et al., High Performance 32nm Logic Technology Featuring 2nd Generation High-k + Metal Gate Transistors, IEDM 2009, paper 28.4, pp. 659 – 662
2. M. Horstmann et al., Advanced SOI CMOS Transistor Technologies for High-Performance Microprocessor Applications, CICC 2009, paper 8.3, pp.149 – 152
3. K-Y. Lim et al., Novel Stress-Memorization-Technology (SMT) for High Electron Mobility Enhancement of Gate Last High-k/Metal Gate Devices, IEDM 2010, paper 10.1, pp. 229 – 232

IEDM 2010 Retrospective – Part 1

The International Electron Devices Meeting started its 56th session last week on Sunday in San Francisco. This year the program appears to more academic than in previous years, and this was confirmed by the conference chair in his opening address – only 145 submissions out of a total of 555, an all-time low as a percentage. Attendance was guesstimated at ~1500, again lower than earlier years on the west coast. On the other hand, the atmosphere is noticeably more upbeat than last year, and there are plenty of industry attendees.

Sunday was short course day, well attended with ~580 participants. There were two courses, “15nm CMOS Technology”, and “Reliability and Yield of Advanced Integrated Technologies” – I sat in on the reliability session and brought myself up to date on the issues now that we’re into the deep nanometer era. The European weather had its effects, the chair Guido Groeseneken was stuck in Amsterdam due to snow, and Werner Weber had to take over. So far Europe has had a worse winter than I’ve had to cope with in Canada!

The course had some useful stuff for me, not being involved in reliability – it’s not something we need to worry about when we take stuff apart! We had a good review of time-dependent breakdown and n- and p-BTI by Ben Kaczer of IMEC; some interesting new analytical work on changes in low-k dielectrics from Shinichi Ogawa; a surprisingly optimistic review of ESD techniques by Christian Russ of Infineon (apparently strain can actually improve ESD performance!); and the day was rounded out by consecutive reviews of different approaches to reliability by design mitigation by Ashraf Alam (Purdue) and Andrzej Strojwas (PDF Solutions).

On the 15-nm course, the gossip I heard was that folks were pleasantly surprised that there is a roadmap to get there. Tom Skotnicki convinced people that the thin SOI/thin BOX solution will work better than finFETs – at least he didn’t get snowed in!

Monday morning we got into the plenary session, starting with Kinam Kim of Samsung. He started off by predicting that DRAM will get into the 10-nm generation, though not for another ten years, by using new variants of MIM stacked capacitors, and evolving through buried wordlines to vertical access transistors with buried bitlines.

Then he moved on to flash, detailing the problems created by a shrinking number of electrons on the floating gate, the increasing aspect ratio of the gate stack, and the inability to scale the dielectrics. We’ll still get to the 1x node, but after that 3D cell structures will appear, likely with charge-trapping technology. We had a brief reference to ReRAM as universal memory (though as the Scots say, I ha’e ma doots), but it’ll be a while before we get there.

Then we moved into logic, with the many variants possible below 20-nm – finFETs, hybrid chips with III-V devices on silicon, graphene, etc, and a quick run-through of the various stacking options such as package-on-package and (of course) TSVs; the latter was apt in the context of the day’s announcement of an 8-GB DIMM using TSVs.

The second plenary talk was equally interesting in pointing up the actual and potential use of semiconductors in making electrical consumption more efficient, from generation through transmission to end usage. Examples given were whole-wafer thyristors used for switching HVDC lines (apparently DC transmission is much more efficient than AC, and there’s a 1400-km, 800KV line in China), and at the other end of the scale a server power supply with 99% efficiency.

Schematic (top) and Image of Whole-Wafer Laser-Triggered Thyristor Switch (Source: Infineon/IEDM)

The afternoon memory session started off with Samsung’s 27-nm NAND flash paper (5.1). It amazes me every time that we see a new generation of NAND flash that the cell is essentially a shrink of the classic control gate/floating gate structure, even though we’re now counting electrons.

That’s what we have here:

Samsung 27-nm (left, source: Samsung/IEDM) and 35-nm NAND Flash Gate Structures

I’ve included an image of the 35-nm cell for comparison, to show the essentially similar structures, control gate/wordline (CG) on top, and floating gate (FG) below. Below is an orthogonal section along the line of the control gate, again with the 35-nm part for comparison.
,

Section Parallel to Control Gate of 27-nm (left, source: Samsung/IEDM) and 35-nm NAND Flash

The main difference we can see, apart form the dimensional shrink, is the increase in the aspect ratio of both gates. This deliberate, to maintain the coupling ratio between the control gate and floating gate, and also the resistivity of the wordline to minimize RC delay (8 ohm/sq is quoted).

One of the changes discussed in the paper is a novel tunnel oxidation process (i.e. between FG and substrate) that conserves the boron doping in the channel and raises the Vt by ~0.5V. This tweak is useful for a number of performance considerations:

• the reduced Vt shift between a programmed state and an un-programmed state helps reduce the capacitance linkage between adjacent floating gates
• it improves endurance by reducing the fringing field between the top corner of the active silicon and the control gate, where it comes down close to the substrate between floating gates – during programming the high voltage across this gap can cause tunneling to the CG, which can degrade the tunnel oxide and affect endurance.
• it improves the data retention by reducing charge leakage off the floating gate

This “novel tunnel oxidation” is not described in detail, but if we blow up their somewhat fuzzy TEM image, and compare again with the 35-nm chip, it looks as though the tunnel oxide has been nitrided.


Tunnel Dielectrics of 27-nm (left, source: Samsung/IEDM) and 35-nm NAND Flash


A question was asked at the end of the paper about the novel oxidation, and of course the presenter didn’t give a direct answer, but an implant step was mentioned; a locking implant for the boron seems likely.

I’ve gone into more detail about this paper than is probably sensible in a blog, but it was the first paper of the regular sessions, and the detail of getting 64Gb of cells that work onto one die can’t help being fascinating to a process geek like me.

Next up (5.2) was Micron’s 25-nm flash, which they announced almost a year ago. A different take on the same challenges, Micron have used air-gap technology to mitigate the capacitance linkage between adjacent gates, and adacent bitlines (see below).

"Air Gaps" in Micron 25-nm NAND Flash (Source: Micron/IEDM)

Essentially they seem to have optimized the uneven fill that we have often see in similar structures (e.g. the Samsung part above), and of course “air-gap” is a bit of a misnomer – I presume it’s actually a vacuum with whtever trace gases are in the deposition chamber when the dielectric is formed.

They also illustrated that at the 25-nm node, we’re down to about ten electrons on the floating gate for a 100 mV Vt shift, so in a typical MLC cell with 300 – 500 mV separation between levels, that’s about 30 – 50 electrons difference. With this degree of sensitivity, any traps in the stack can affect the Vt, so considerable effort has been taken to minimize trapping and charge leakage.

Electrons required for a 100mV Vt shift vs. cell feature size. 
(Source: Micron/IEDM)

Micron also highlighted the sensitivity to boron concentration in the channel – instead of counting electrons, we’re counting atoms – at 25 nm we’re down to ~75 atoms, with a 3σ variation of ~35%, and a corresponding effect on Vt; together with the increased sensitivity to noise at this node, some serious work has had to be done on the programming algorithms and error correction.


Number of Boron atoms per cell vs. feature size.
(Squares - mean; diamond - -3σ; circle - +3σ; triangles - ±3σ percentage divided by the mean. Source: Micron/IEDM)

Later in the afternoon Macronix had a couple of papers (5.5, 5.6) on the other flash technology, charge trapping (CT) using a nitride layer. Macronix has been one of the more prolific industrial contributors in recent years, with six papers this year and seven last year.

Coincidentally, the first paper is on a BE-SONOS NAND flash structure (barrier-engineered SONOS), which uses a thin ONO layer under the charge-trapping nitride layer, instead of under the floating gate (as we speculate above, in the Samsung paper). The thin ONO layer is used as a “modulated tunneling barrier”, which suppresses hole tunneling at low electric fields for retention, but allows efficient tunneling at high fields for erase.

That gives us a ONONO stack under the gate;

Orthogonal Sections of Macronix 38-nm BE-SONOS NAND Flash
(Source: Macronix/IEDM)

The detail in the paper reveals that the lower two oxides are actually nitrided, and the ONO barrier layer thicknesses are 13/20/35 Å (bottom - top), covered by a ~70 Å nitride layer and another ~70 Å oxide, formed by oxidizing the nitride layer. 75-nm and 38-nm NAND flash structures were tested.

The intent of this work is to show that the reliability is improved by leaving the dielectric stack intact, as opposed to etching it when the gates are etched; previously it had been thought that the CT layer had to be etched to stop charge spreading on the nitride. In this they seem to have succeeded, since there is no change after a multiplicity of cycling tests, too many to go into detail here. The results indicate that there is no lateral charge spreading on the nitride CT layer.

Since the CT dielectrics do not need to be cut, this avoids any in-process damage at the edge of the dielectric; an advantage over the cut-dielectric version of CT-flash, but also over floating-gate flash, since these days the floating gate and STI are defined simultaneously, and the FG edge and tunnel dielectric are vulnerable.

The other Macronix paper (5.6) details a study of fast initial charge loss in CT-flash devices, incuding BE-SONOS, where the Vt shifts within a second of programming, and then saturates at a stable value. They minimised this by optimizing the film stack, and by refill programming to duplicate program levels.

Macronix has done a lot of work on the different CT-flash technologies, but BE-SONOS seems to be particularly pragmatic form, and a viable alternative to FG-flash – will we see it in production any time soon?

That was the end of day 1 of the conference; there were other papers that I missed, but I will be trying to review them in the next few weeks; meanwhile part 2 of IEDM retrospective will be up in a few days, covering the final two days of the meeting.

IEDM Next Week!

Next Sunday the great and the good of the electron device world will be gathering in San Francisco for the 2010 IEEE International Electron Devices Meeting. To quote the conference web front page, “IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices.”

From my perspective at Chipworks, focused on chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.


In the last few days I’ve gone through the advance program, and here’s my pick of what I want to try and get to, in more or less chronological order. As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.

On Sunday December 5th, we start with the short courses, “15nm CMOS Technology” and “Reliability and Yield of Advanced Integrated Technologies”. Kelin Kuhn of Intel has organised the former, and we have some impressive speakers – Thomas Skotnicki (ST – Trends and Scaling), Mukesh Khare (IBM – Device Challenges), Sam Sivakumar (Intel - Lithography), Yoshihiro Hayashi (Renesas – BEOL), and Clive Bittlestone (TI – Device/Circuit Interactions).

Having started in the business on 10-micron geometries, 15-nm devices seem crazy to me, but on the Intel clock it’s only three years away! I’m starting to tell folks to think about the end of silicon, at least as we know it, since my brain will not wrap around the idea of 11- and 8-nm gates, and 11-nm is only five years away (and 30 – 40 atoms across, depending on orientation!). The guys in the R&D labs have been thinking about that for the last decade or so (as we’ve seen at IEDM), so this should be an interesting day to see what they’ve come up with and how we get there.


The other side of the technology coin is reliability at these advanced nodes, and IMEC’s Guido Groeseneken has set up the other short course, with a slightly more academic slate of instructors. We have Ben Kaczer (IMEC – FEOL), Shinichi Ogawa (NIAIST – BEOL), Christian Russ (Infineon – ESD), Ashraf Alam (Purdue – Reliability-Aware Design), and Andrez Strojwas (PDF Solutions – Yield, Yield models, and DFM). Another good day – although the courses make a long Sunday, from 9 a.m. to 5.30 p.m., it’s worth sticking around to the end.

Monday morning we have the plenary session; a couple of good ones here, kicking off with Kinam Kim of Samsung, discussing silicon’s future (will it get beyond 11 nm?) and Arunjai Mittal of Infineon will discuss potential energy savings through the use of semiconductors – energy efficiency is one of the major themes of the conference this year. The third plenary is on bionanoscience in healthcare, a whole new area to me; the plenaries traditionally make the link between semiconductors and other fields of science.


After lunch we get to the conference proper. Straight into session 2, we have a set of 3D integration papers, by TSMC (paper 2.1), on integration at 28 nm, TSV-induced stress on HKMG (high-k, metal-gate) devices by Panasonic/Qualcomm/Samsung/IMEC/Newcastle U (2.2), and IBM (tungsten TSVs – 2.4), and some more academic institutions.

Session 5 on memory technology is split between traditional floating gate flash papers by Samsung (5.1) and Intel/Micron (5.2), and charge-trapping MONOS/SONOS flash, with two papers by Macronix (5.5, 5.6). Micron and Samsung are touting their 25 and 27-nm (respectively) NAND flash technologies; Micron has solved the interline capacitance (wordline/wordline and bitline/bitline) problem by using airgaps:



Micron 25-nm NAND Flash - X-Sections of Wordlines and Select Transistors (top) and Bitlines (bottom) Source: Micron/IEDM

To my knowledge this will be the first volume production of air-gap technology in any product, even though there have been announcements by IBM and others discussing its use in the metal-dielectric stack. It’s kind of ironic that this is in the process front end! Laura Peters has been previewing a number of IEDM papers at ElectroIQ, and more details of this one can be found here. We’ll see how Samsung gets around the same problem…

There’s also a paper from NCSU (5.3) discussing TaN floating gates down to 1 nm thick; if it works it will be a step towards vertically shrinking the NAND flash stack, something that hasn’t happened much so far in the conventional two-polySi gate structure.

Intel have a couple of papers (6.1, 6.7) indicating where they may go at the 15- and 11-nm generations; both detailing Quantum-Well Field Effect Transistors (QWFETs), the former InGaAs finFETs, and the latter strained germanium pFETs.

Come 6.30 there’s the reception, a chance to see folks we haven’t seen since the last year, or at least since Semicon West, the last tech-fest I was able to get to. Bring ear-plugs – a thousand-plus engineers talking at the same time make a lot of noise!

Tuesday morning there’s a session on high-k and channel engineering, with the IBM Alliance tuning pFET VTH with a Ge implant (11.4, Laura’s take here), and TSMC/Nanyang U discussing gate stack annealing in their gate-last process (11.6, Laura)

Session 12 features another group of memory papers; Hynix is giving an invited review paper (12.4), and is co-affiliate with Grandis on a spin-torque RAM (12.7); and IBM (12.5) and Samsung (12.6) have papers on the same topic.

Session 13 is a highlight session of invited papers on “Next Generation Power Devices and Technology”, covering the field from silicon and silicon carbide to gallium nitride devices.

In the field of image sensors, TSMC has an invited paper (14.1) on a 0.9 µm pixel BSI (backside illumination) image sensor and the scaling challenges involved. TSMC fabs the sensors for Omnivision, which are now at the 1.4 µm BSI generation commercially, so maybe we’ll see this one in a couple of years. Omnivision has now migrated to a 300-mm copper process for their 1.1 µm pixel part, just being launched. This is how we get 12-Mpixel cameras in a cell phone!


Cross-Section of Omnivision OV5642 1.4 µm-Pixel BSI Image Sensor

The IEDM conference lunch speaker is Jim Clifford of Qualcomm, on the evolution of their chipsets and the technology required – we have just seen their first 45-nm part, and they are leaders in multichip packages; maybe we’ll get a hint of their 28/32 nm and TSV plans.

Macronix has a third paper (19.2) in the afternoon memory session on tungsten oxide resistive memory; and in the power session Panasonic (20.5) describes a high-voltage (1300+ V) AlGaN/GaN on silicon device, and TSMC talks high-performance LDMOS (20.8). In general the afternoon has a preponderance of academic speakers, with other sessions on device/circuit interactions, advanced processes, thin film transistors, memory simulation, and graphene (sessions 17, 18, and 21 – 23).

At 5.15 we have the first of three sponsored events; Applied Materials is holding a technical symposium, “Is Moore's Law Taking Us in a New Direction? The Future of Transistor Technology”, around the corner at the Wyndham Parc 55 hotel, with a slate of speakers from GLOBALFOUNDRIES, IBM, Qualcomm, ST and other companies.

And if that’s not enough, there are the conference panel sessions back at the Hilton at 8 p.m. – “Heterogeneous Device Integration as Enabler of Functional Diversification for More than Moore”, which promises to range from nanomaterials to 3D chip stacking; and “Power Crunch - Threat or Opportunity?”, discussing power optimization at the transistor, circuit, and system level.

By the end of those (if I’ve lasted that long) I will surely be getting into information overload, so I hope I sleep well, ready for session 27 on Wednesday morning, which covers off the advanced HKMG CMOS papers.

TSMC are discussing 22-nm FinFET process (27.1), Intel (27.2) have a HKMG RFCMOS review, Qualcomm (27.3) are talking 28-nm low-power SoC technology (gate-first or gate-last – we’ll see!), and IBM (27.5) are updating the 32-nm eDRAM work they presented last year. The odd paper out (27.4) is a more theoretical study by Texas Instruments of the way 1/f noise is affected by layout features such as active/active spacing and dual stress liner boundaries.

Cross and Longitudinal (right) Sections of TSMC 22-nm FinFET (Source: TSMC/IEDM)

In the parallel sessions Renesas is detailing microwave annealing of NiPt silicide (26.1), STMicroelectronics et al.(29.1) and NXP-TSMC (29.2) have phase-change memory papers, and Hynix (29.7) is showing off a 3D NAND-flash memory cell.

Lunchtime, ASM is holding their fourth annual seminar with their own speakers and Mike Chudzig from IBM, on ALD and epitaxy in CMOS.

Afternoon session 33 (novel processes) kicks off with an invited talk by Ichiro Mori of SELETE (33.1) on their EUV results; I’m not sure the concept of EUV is novel any more, but it’ll be interesting to see how far things have come.

Renesas has a paper on embedded DRAM with MIM capacitors in porous low-k (33.3), continuing the technology we have seen from the former NEC in the Nintendo Wii – now in volume production in their 55-nm process.

Embedded DRAM Capacitor Stack in NEC-Fabbed Memory Die From Nintendo Wii


A little later there is a talk by the IBM consortium on 32 nm BEOL using copper with a copper/manganese seed layer (33.5), followed by TSMC (33.6) discussing chip/package interactions when extreme low-k dielectrics are used.

In parallel sessions, TSMC have another FinFET paper (34.1), and a breakdown study of low-k dielectrics (35.2). Toshiba have an interesting failure analysis study (35.3) looking at anomalous phosphorus diffusion by scanning spreading resistance imaging, followed by U. Cal, IMEC, and Infineon (35.4) examining the effect of strain on ESD protection devices. Laura P. adds detail at ElectroIQ here.

By Wednesday afternoon a lot of attendees will be heading for home, and I’m usually thankful when the last paper’s done, but that’s not the end this year! The SOI Industry Consortium is holding a workshop on fully depleted SOI starting at 5 p.m., with some notable speakers from academe and industry. It will be in the Hilton, preceded by a reception and followed by a buffet supper to aid the weary bones and brain cells.

So as always, no peace for the curious! I will be trying to post a more detailed blog as the conference unfolds, but given all the interesting topics being covered, time may be at a premium. I hope to see you there!

TI Ships 40-µm Fine Pitch Copper Pillar Flip Chip Packages

The week before Semicon West, Texas Instruments and Amkor released a joint announcement that they were shipping parts in fine pitch copper pillar packages. Mark Lapedus at EETimes picked the story up and added the detail that the latest OMAP processors were going out in this format.

By coincidence, Chipworks had just finished analysing TI’s Sitara AM3715, a 45-nm applications processor with a 1-GHz ARM Cortex-A8 core and a POWERVR SGX™ Graphics Accelerator within (it seems to be a re-purposed OMAP3630, since the die marks are almost the same); and it turns out that it is packaged using this technology.

It had attracted my curiosity when we received the part, since the customary x-ray that we do looked odd – no wirebonds, and no C4 solder balls – so we did a section, and lo and behold, this is what we see, in Fig. 1:

Fig. 1 Cross-Section of Texas Instruments XAM3715

This is the first time we have seen copper pillar technology since Intel adopted it a few years ago, but the style is different. Looking closer (Fig. 2), we can see that the plugs are tapered with some solder flow down the side, and it appears that the copper traces had been pre-coated with the same tin-based solder (likely SnAgCu).

Fig. 2 Close-up of Copper Pillar Bumps

The substrate is four-layer with two built-up layers (1-2-1), and the trace pitch is ~40 µm; in this section the pillars contact alternate traces, since the bond pads are staggered (Fig.3).

Fig. 3 Plan-view Image of Bond Pads

Amkor published two papers [1, 2] at last year’s IITC and ECTC which together seem to describe the process. Copper pillar bumps with solder caps are formed on the wafer (Fig. 4) and the wafers are thinned, in our case to ~90 µm, and then singulated.

Fig. 4 Amkor Copper Pillars [1, 2]

Non-conductive paste (NCP) is pre-dispensed on the substrate and the die is thermo-compression (TC) bonded onto the substrate (Fig. 5).

Fig.5 Amkor NCP + TC Process Flow and Result [2]

One difference that we noticed in the Sitara chip was that the pillar bumps were oval, as seen in the footprints in Fig. 3. Fig. 6 shows a section at right angles to Fig. 2, and we can see the elongated profile of the pillar and the bond pad above, with a via going to a copper metal line above that. In Fig.2 we also see some leakage of the solder down the sides of the pillar, maybe a function of the TC process using an oval shape.

Fig. 6 SEM Cross-Section of Pillar Bump

It appears that TI and Amkor have been using these pillar bumps for a while, since our sample was dated December last year. In the meantime, we have seen the OMAP3630 in Motorola’s new Droid X and Droid 2 phones, so they have assuredly hit high volume production.

References

[1] Lee, C., Interconnection with copper pillar bumps: Process and applications, IITC 2009, pp. 214-216.
[2] Lee, M. et al., Study of Interconnection Process for Fine Pitch Flip Chip, ECTC 2009, pp. 720-723.

Non-Intel HKMG Coming Soon? And 45LP Makes the Mainstream in Mobiles

The last few weeks have seen some announcements that finally seem to show that HKMG (high-k, metal-gate) processes other than Intel are coming into the real world.

First, on September 7, Samsung showed off an engineering sample of their 32-nm Saratoga chip at their Mobile Solutions forum. A week later on the 15th, Panasonic declared that in October they would be shipping 32-nm HKMG chips for use in Blu-ray disc players. And at the end of the month Altera launched a video on their website demonstrating the transceiver performance of their upcoming 28-nm Stratix V FPGAs, so they now have real silicon to show off, fabbed by TSMC in their gate-last HKMG process.

So things are hotting up; after almost three years, we seem to be in sight of the next HKMG product. Based on the 45-nm launches, I would put my money on Panasonic. Matsushita, as they were then, made a product announcement about having their 45-nm Uniphier chip in a Blu-ray player, and it appeared when they claimed it would. In fact it was a few days earlier than the Intel 45-nm part, back in November 2007, and remarkably we bought our Blu-ray player (in Japan) for teardown only three weeks after the part was packaged – talk about a just-in-time supply chain!

Panasonic have been remarkably quiet about their 32-nm process development, after being almost synchronous with Intel for the 65- and 45-nm generations. They have had a joint development agreement with Renesas since 1998, and in 2008 re-iterated that for 32-nm development. In September last year they announced that the joint development would continue at Renesas’ Naka site, and that they had solidified the HKMG and ultralow-k dielectric processes enough to set production dates.

Historically, Panasonic/Matsushita have appeared to focus on process shrinks for cost-reduction and SoC integration purposes, and not pushed the performance techniques as Intel did, such as enhanced strain. Changing to HKMG is a bigger stretch than shrinking a polysilicon gate process, so taking a year longer is not surprising.

The only other contender for a high-k (not metal-gate) process coming into production was NEC’s 55-nm HK variant, launched [1] some three years ago. I’ve been watching for this one since then, but while we’ve found 65-nm and 55-nm (even with embedded DRAM), we haven’t found the high-k version. I’m a bit reluctant to admit it’s vapourware, but it looks that way, especially as NEC (now Renesas) are talking of their 45-nm non-HK product.

So, we’ll see – in the meantime, Intel is steaming ahead and it looks as though they will have their 22-nm process in production on schedule in Q4 next year. We are currently anticipating their 45-nm SoC product, to see what the differences are with the 45-nm Xeons that we looked at three years ago.

Compared with previous generations, the 45-nm rollout has taken a while, particularly for some of the low-power variants. They are showing now, though, starting with Samsung/Xilinx and the higher profile A4 chips Samsung fabbed for the Apple iPad/iPods, and the UMC-fabbed TI OMAP3630 chips in the Motorola Droid series of phones.



Transistors from Apple/Samsung (left) and TI/UMC 45-nm Low-Power Chips


Strangely, TSMC announced volume production of their 40LP process in November 2008, but we have only just encountered it in a commercial product. TSMC have had well-publicised yield problems on high-end parts, but they still shipped product for Altera, AMD, nVidia, etc; it seems odd that the less complex LP product (less strain, no e-SiGe) would take longer than the GP product. It makes one wonder if leakage has been the problem with the LP variant, since it has a direct effect on battery life in mobile applications, and what is acceptable in a PC gaming system would be useless in a cell-phone.

On the CPU/GPU front, of course, 45-nm product is well established, both in PCs and other systems such as the Xbox and Playstation 3. Still, it’s been almost three years from the first 45-nm part to the latest introduction; in industry terms, maybe Moore’s law is slowing down!

[1] F. Tadashi et al., A New High-k Transistor Technology Implemented in Accordance with the 55nm Design Rule Process, NEC TECHNICAL JOURNAL Vol.1 No.5/2006 pp. 42 – 46

Samsung’s Eight-Stack Flash Shows up in Apple’s iPhone 4

Back in 2005 Samsung made an announcement that they would be shipping eight die stacked in the same package. At the time it seemed remarkable, but we didn’t see it any time soon after that, so it got lost in the noise of other package developments and the increasing TSV (through-silicon vias) hype.

Last year we commented, in the now defunct Semiconductor International, on a 16GB Sandisk Micro-SD flash card that had nine die stacked together, thinned to a remarkable 30 µm each.

Sandisk 16 GB Flash Stack in Micro-SD Card

Now Samsung have delivered, in the new iPhone; our 32-GB version had one Samsung flash part within, a K9PFG08U5M (below), which their part number decoder reveals as a 256 Gb MLC (multi-level cell) NAND flash device.

One digit decodes as ‘ODP’, which isn’t clarified, but once the chip was taken off the board and x-rayed, we could see eight dies, so octal-die package seems to work. It doesn’t show up too well in plan-view, but a side-view x-ray makes it clear enough:

So, having seen the x-ray, I asked one of our lab guys to see if he could section one of the wire bond stacks that we can see in the above image. The bonds at opposite ends of the package aren’t in the same plane, so we can only get one set of bonds, but to me he did a pretty good job.

The package, including substrate, is ~0.93 mm thick, and the die stack is ~670 µm high. Die thicknesses vary from 55 – 70 µm, with the thickest die at the bottom. Thinner than the 1.4 mm announced in 2005, and not quite the 0.6 mm quoted in last year’s ‘ultra-thin’ release, but impressive nonetheless.

What surprised me, when I looked closely at the section, was how close to the top surface the top wirebond loop is – that’s 25-µm wire, so it looks to be less than 10 µm from surface – that’s minimising encapsulant for sure!

Every time we tear down something like the iPhone, it is clear that it’s not only the chip technology that makes these toys possible; they wouldn’t be the same without the parallel developments from the TAP part of the business, not to mention the software.

Still, as with the Sandisk, it poses the question: If we can build stacks of dies like this with wire bonding, will through-silicon vias ever become economic in the commodity chip arena?