Dialog Semi Gets the Girls for Apple

Over the years we have looked at a number of products from Apple, and in their mobile products we have seen a continuous series of design wins for power management chips from Dialog Semiconductor, all custom-made parts since they have not been in their normal product listings. 

One of the distinguishing features of each part has been the code names Dialog has used for them - as my colleague Jim Morrison has noted, they are all girl's names starting with A! Now read on..

Contributed by Jim Morrison

When it comes to Apple, the letter “A” features very prominently at Dialog Semiconductor.

Why, you ask? Every time we take a look at the power management ICs in Apple products, we find another Dialog Semiconductor device that has been named with a female first name, beginning with “A,” as we previously blogged about with Dialog Semiconductor's design win in the iPad 2.

Our most recent examination of the iPad 3 revealed Amelia in the PMIC for Apple's newest tablet.


Amelia (D1974A) from the New iPad

Does Dialog like to code their products so that all devices developed for Apple begin with A? Does renowned secrecy at Apple require all suppliers to be so hush-hush that to avoid errors, they talk about Apple using code names? Or does the power management team at Dialog just have a thing for female first names beginning with "A"? Perhaps the design manager has a family of daughters that all have names beginning with A. My family is all names with J so it’s quite possible another family has all As.

The iPhone 3 and 3GS liked Amanda, the iPhone 4 and the iPad 1 liked Ashley (Dialog Semiconductor D1815A), the iPhone 4s has Angelina, Dialog Semiconductor D1881A (my favourite), the iPad 2 has Alison (Dialog Semiconductor D1946A), and now our iPad 3 has chosen Amelia.

Amanda (D1755A) from the iPhone 3 and 3GS



Ashley (D1815A) from the iPhone 4 and the iPad 1



Angelina (D1881A) from the iPhone 4S



Alison (D1946A) from the iPad 2

 These die markings are changing because the die design has changed to accommodate new power requirements as we went from A4 processors to A5 to A5X, and other modifications in products that required changes to the PMIC.

We will see if the series continues in the iPhone 5 expected in the next few months..

Semicon China – SMIC Shows off 28-nm HKMG Development

Another foundry goes gate-last

In the opening keynote at Semicon China today, Dr. Tzu-Yin Chiu, CEO of SMIC, gave a run-through of their technology portfolio, and in doing so let out a few details of their sub-40 nm process development.

SMIC's Process/Application Portfolio

It appears that they are actually shipping some 40-nm pilot product for revenue, and to keep the ARM-world happy, they will have Cortex A9 cores running at 1.2 GHz by the end of the year.

Snapshot of advanced nodes at SMIC

Scheduled for mid-2013, their 28-nm offering will be both high-k, metal gate and poly/SiON, and feature one of the smallest SRAM cell sizes to date.

SMIC's 28-nm schedule

The images are all distinctly fuzzy thanks to the challenges of using a phone camera at some distance from a dimly-lit screen, but they show what I’m talking about. It appears that the gate-last structure has more in common with TSMC’s 28-nm structure than Intel’s 32-nm, and also that the NMOS and PMOS labels have been reversed.

SMIC 28-nm transistors and SRAM cell

In all the other gate-last HKMG transistors we have seen, the thick TiN and Ta layers are in the PMOS (you have to squint to distinguish them in this image, but they are there), and I wouldn’t expect SMIC’s to be any different. We can also see the tell-tale notch at the base of the transistors that indicates that the gate dielectrics were formed before the dummy poly gate was put down.  At less than 0.13 sq. microns the SRAM cell is the smallest that I know of – TSMC is 0.15, and Intel 0.17 sq. microns.

Just for comparison, here’s a pair of composite images of Intel’s 45-nm transistors and TSMC’s 28-nm transistors. You can clearly see the notches at the bottom of the gate structures that I refer to above.

Intel 45-nm transistors (left) and TSMC 28HPL transistors

The inclusion of a poly/SiON variant (presumably low-power) at 28 nm puts them on a par with TSMC and UMC, and leaves GLOBALFOUNDRIES as the only major foundry without an announced non-HKMG LP process at that node. If the rumours about GloFo second-sourcing the Qualcomm S4 (currently on TSMC’s poly/SiON 28LP line) are true, presumably they’ll have to develop one!

GloFo’s FinFETS are Better than Intel's! Musings from CPTF

This confident statement came from Subramani (Subi) Kengeri of GLOBALFOUNDRIES (GloFo) during the panel session in the GloFo/IBM/Samsung Common Platform Technology Forum (CPTF), held Wednesday in the Santa Clara Convention Center. I’m currently on one of my periodic road trips, and this one has given me the chance to sit in on the CPTF – last year I had to make do with the online version.

Towards the end of the panel discussions, the host, Jaga Jagannathan of IBM, asked Subi “How do you stack up against Intel? – especially in the SoC/smartphone space?” This clearly took Subi by surprise, but after some preamble, he focused on FinFET development, which AMD, then GloFo, have been working on for the last ten years.  In conjunction with customer input, they have been focusing their finFET efforts to optimise the (14 nm) process for mobile SoCs. He said that this was what would differentiate them from Intel, and in that space “We believe we have a much better finFET, that is optimised for mobile SoCs”.

CPTF panel session. Jaga is on the left, and Subi third from the right.  Source: Common Platform

Of course time will tell, and the CPTF 14-nm process will likely not show up for three or four years, while we are waiting for Intel’s imminent launch of their trigate product.

The panel session has been put online, so you can see it by going here, register if you need to, then select Agenda and click the relevant link; if you want to see this particular Q & A, move the slider to the 52:30 timepoint.

Also during the discussion Subi stated that GlobalFoundries is in production for 32-nm HKMG, and running the full flow of the 20-nm (gate-last) process in their Malta NY fab.

Earlier in the day he had given one of the keynote talks, and it was then that he gave the logic for the move to finFET at 14-nm that was a major theme of the day.  It boils down to the fact that by the time you get to the 20-nm node, there are no more knobs to turn to crank up the performance of a transistor.  In order to mitigate the short-channel effects and increase drive current, a 3D fully-depleted structure is needed. GloFo regards the mobile sector as one of the big drivers for leading-edge process development these days, so their finFET efforts have been focused in the mobile SoC arena, with a multiple Vt process in development.

Another nugget from the day was the public announcement that Samsung is in full production with their 32-nm HKMG process, and it appears in Austin as well as Korea.  I was hoping that we might see it in the new iPad, but we’ve now confirmed that the A5x chip is 45-nm. I guess we’ll have to wait for one of the new phones or tablets that will be out soon. Actually, that includes TVs too – Samsung had a TV with gesture recognition on the show floor, powered by a 32-nm HKMG processor, and that’s due out next month as well.

The following day I was at an Intel analyst meeting, but that’s under NDA so I can’t say too much; but it’s not letting too much out to say that it reinforced their messages from CES and the Mobile World Congress that there will be a big push on Ultrabooks and mobile phones.  Next month expect a huge marketing campaign for Ultrabooks – it was described as “epic” and “cinematic” at CES. Even now we’re seeing all sorts of product announcements by the OEMs, including plenty with the 22-nm Ivy Bridge chip inside.

At the moment I’m in Shanghai taking in the China Semiconductor Technology International Conference and Semicon China. I’m presenting on “Recent Innovations in Leading-Edge Silicon Devices”; hopefully it will get a good reception. And we’ll see if there’s anything blog-worthy this week. In the meantime I tweet @ChipworksDick if anything is noteworthy.

GLOBALFOUNDRIES' Ajit Manocha Visits Vegas for CES

GLOBALFOUNDRIES has hosted a reception for the last three years at CES, although they don't exhibit there, or even take a suite for the show - they find it a useful way to connect with customers and the analyst and journalist community. Held on CES Tuesday (Jan 10), I expected a large Intel-style gathering with lots of flash, but it was actually quite low-key in a hospitality suite at the Mandalay Bay resort, with no more than thirty people there at any one time.

After the initial introductions, Ajit stood up and gave a short speech celebrating the first silicon coming out of Fab 8 in Malta, New York, as announced that morning - the first wafers squeaked into 2011 as promised, coming out of the line on 27th December; and we can expect the first 20-nm silicon in June. He also spoke of the recent management changes and plans for $3 Bn capex for 2012 revealed in an interview the same day, bringing the total capex for the last three years to almost $12 Bn, showing their commitment to stay the course in the industry. He emphasised that "GLOBALFOUNDRIES is not just Dresden", and that the former Chartered Semi fabs in Singapore were contributing significantly to GloFo's bottom line.

Ajit Manocha at GLOBALFOUNDRIES' CES reception

The roster of customers that were present supported that, since most were fabless companies with product using larger node processes than the 45- and 28-nm product from Dresden.  Notably, AMD were not present, at least when I was there. A good crew of GF management was there, Kevin Kimball (VP, Global Communications), Mojy Chian (Senior VP, Design Enablement), and his colleague Derek Meyer, and Subramani (Subi) Kingeri, (VP of Design Solutions - 14nm), amongst others. There were a couple of wafers on show too, unfortunately not from Fab 8 - that would have been really topical!

28-nm and 32-nm AMD Llano Wafers from GLOBALFOUNDRIES Fab1 in Dresden

GloFo is clearly staffing up at Fab 8 - they held a job fair there last week and reportedly have hired 1100 so far, heading for 1400 by year end. By the look of some of their stock photos, they are still not 100% functional yet, but it obviously won't be long!

GloFo shot of Fab 8 clean room - note the hard hats and hand-carried FOUPs!

Aerial shot of GLOBALFOUNDRIES' Fab 8 in Malta, New York

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Intel Press Briefing and Keynote at CES 2012

Intel UltraHypes Ultrabook at Monday's Press Briefing

The Intel press session Monday morning at CES was focused exclusively on the Ultrabook, with Mooly Eden hyping up this supposedly new category of laptop. He prefaced the talk by saying there would be no discussion of 22 nm, Ivybridge, or any new silicon; the emphasis would be on "experiences" achieved by Ultrabook, not just speed and performance as Intel has done in most of the last few years.

Having said that, he went through an impressive array of the different applications that we use these toys for - games, internet, raw computing (as in graphics manipulation), and demonstrated the added security that they've built in since incorporating McAfee last year.

Mooly Eden and Associate at Intel CES Press Briefing

We then had a series of different versions of Ultrabooks, some of which were like the old HP systems where the screen could be flipped to turn it into a tablet (only these days with touchscreen). One of the most interesting had a small additional touchscreen on the lid, about 2" wide and the length of the laptop, so that it could be accessed without opening up and powering up the whole thing.  A concept  at the moment (Nikiski, I think it was called), but to me it had potential.

Of course, now that we are in the days of Apple's Siri, speech recognition has to be on the horizon, so Mooly announced a partnership with Nuance and their Dragon system, and brought out their CEO for a few minutes of mutual congratulation.

Gesture recognition is also the coming thing, so we had a demo of that,which evolved into a plug for the sheer computing power of the Sandybridge/Ivybridge parts and what they can do.  Apparently there are more than 75 Ultrabooks coming onto the market this year, with screen sizes from 11 - 15", and at "affordable" prices.

Then the VP of Marketing and Sales came onto the stage, and announced a change in marketing approach from speed and performance to experiences, as Mooly had said earlier. They will be doing a huge marketing campaign partnering with a whole lot of companies, more than just those branding the Ultrabooks. This will start in April - described as "epic', and "cinematic".

There was a mystical announcement made that Paul Otellini will have some significant statement to make at Tuesday's keynote, and then we got to the "piece de resistance" of the show.  Intel are "seeding" Ultrabooks to the media, and fifty lucky folks found white envelopes under their chairs, containing an Ultrabook - theirs to keep provided they play with them and write about the experience.  Needless to say, the room went crazy, and I wasn't one of the lucky ones! The rest of us do have a chance; apparently if we email ultrabookseeding@ogilvy.com with a good story on how we can promote Ultrabooks, they have some more to hand out.  We'll see!

So to sum up, Ultrabooks are going to happen bigtime this year according to Intel, and not entirely to my surprise, there was no talk of a launch of any 22-nm product.  I did ask one of the guys there if there was a launch date, but all he said was that there would a phased launch in the spring, based on application - I think we'll see mobile product coming out first.

Stay tuned for that one, as soon as we get analysis started we'll let you know!

CES Keynote:  Intel in Lenovo Phone and Tablet, Partners with Motorola Mobility

At Tuesday's CES keynote, Intel CEO Paul Otellini announced that there will be an Intel processor in a Lenovo phone, coming soon, and a new partnership with Motorola that will bring more Intel presence in the mobile arena.

After some initial preambles about the ubiquity of personal computing, and confirming that the 22-nm Ivybridge is now shipping (with a line-of-sight to 14 nm), we got to the first of the "mystical announcements", and he invited Liu Jun on to the stage. Liu is a Senior VP of Lenovo, and President of the Mobile Internet and Digital Home Group, and he came up to announce the launch of the Lenovo K800 smartphone, to be shipped in Q2 to China Unicom.  It's using a version of the Atom processor, has a 4.5", 720p screen, runs Android, and has 8 hours of talk time and 14 days standby time.

Liu Jun and Paul Otellini show off Lenovo K800 Smartphone, powered by Intel

Not too many other specs were discussed, so we'll have to wait until the phone surfaces in China for a more detailed look. Liu also briefly brought up a 10" tablet using a 32-nm Atom processor, but no extensive demo there.  There was an extensive demo of an Intel reference phone, which was impressive, but then one would expect it to be in a keynote talk. Later on there was also a brief showing of a reference tablet running Windows 8.

Next up was Sanjay Jha, Chairman/CEO of Motorola Mobility, and they announced a multi-year partnership focused on making Intel-based devices, with the first phones coming out in the second half of the year.

Now we get a sequence of visitors to the stage; first Chris Aubrey of Adidas, selling running shoes using an Intel-based video wall ( a big push for the Olympics in London), and then Jeff Clarke  of Dell, launching their XPS13 Ultrabook. This looks very sleek, and can be ordered now, available in February, which presumably means it's based on 32-nm Sandybridge, not 22-nm Ivybridge.
After some showing off of the laptop/tablet convertible that Mooly Eden had on Monday, a couple of Intel staffers traded apps on a pair of Ivybridge-based Ultrabooks, which at least proves that they are out there and I presume at least some OEMs are getting silicon.

The final visitor is Will.I.Am, talking about making music on an Ultrabook, writing a new song for every city while he's on a world tour to raise money for inner cities (at least I think that's what he said - he didn't exactly look comfortable on stage taking techie questions). He finishes by holding the Ultrabook on his shoulder and announcing "the Ultrabook is the new blaster!"

Will.I.Am looking out of place while clutching Ultrabook

Then a post-amble about the spread of transistors and computers and we're done - off the stage, no questions asked.  Summing up - Intel is getting into the mobile space (probably slower than they'd like), Ivybridge is coming, and watch out for Ultrabooks.

TI Debuts 28-nm OMAP 5 Processor at CES

This year, for the first time I made it to the International Consumer Electronics Show (CES) in Las Vegas. To say it is an endurance test is putting it mildly - close to 150,000 attendees predicted and ~5,000 media/analysts, so we (there's two of us from Chipworks) spend more time standing in line than actually seeing the show.

Be that as it may, Tuesday morning we went to one of TI's suites at the show, and lo and behold, a working OMAP5430! Announced last year, this is something we've been anticipating at Chipworks for a while. The silicon came out of the fab two or three weeks ago and is going through phase one testing, but so far it's "live, stable and 100% functional". Testing has gone well enough that samples are already in customer hands.

There was a mobile demonstration unit showing graphics processing at 64 fps (using Android's Ice Cream Sandwich), which compares with 47 fps for the OMAP4470. Other exercising is obviously being performed, but the space was pretty crowded so we didn't get a chance to get an exhaustive display.

There was a palpable feeling of achievement in the room, and the folks showing us around were like new parents - great to feel that buzz! Given that Huawei just announced a phone with the OMAP4460 in it, things are going well for TI.

It's too early to have a great deal of detail (so no pictures!), but essentially the part is meeting the published specs, and on track to be a 2GHz processor.

Fabbed in UMC's 28LP process, it utilizes two ARM Cortex A15 cores, and two low-power Cortex-M4 processors (taking the "big-little" approach discussed at the ARM Techcon last year). It has 2 MB cache, and the graphics side is covered by dual POWERVR™ SGX544-MPx graphics accelerators.

Initially it will be shipped in a 14 mm x 14 mm PoP with 980 balls on 0.4mm pitch, and the stock photo below looks remarkably like the Amkor Thru-Mold Via technology that we first saw with the OMAP4430 in the RIM Playbook.

TI Stock Image of OMAP 5 Platform

Given that first silicon is only just out, it's unlikely that we'll see the 5430 in a downstream phone or tablet for a year or so, but who knows, if things pan out well, some OEM may want to accelerate that and we'll get it earlier.  I hope so!

Thanks to Brian Carlson, Mike Blaskovich, and Heather Ailara for hosting us and letting us be among the first to see this hot new device.

We have been posting blogs from CES, mostly commentaries on the press sessions so far, at our Chipworks blog, and follow my occasional tweets at @chipworksdick.

IEDM 2011: IBM displays via-middle TSV process for die stacking

A few days after IBM and Micron publicized their hybrid memory cube, IBM gave their TSV paper at IEDM on the Monday afternoon (paper 7.1).

Entitled "3D Copper TSV Integration, Testing and Reliability," they described a node-agnostic through-silicon via (TSV) technology which takes a via-middle configuration, making contact to the upper metal (fat-wire) layers in the device structure. By "node-agnostic" they mean that they proved the concept in devices fabbed on processes ranging from 90nm down to the 32nm HKMG process. In doing so, the TSVs have anything from three to nine metal layers below the contact level, and have to cope with dielectric k-values from 4.1 down to 2.4, and bulk and SOI wafers.

The paper doesn't specifically say so, but it appears that the TSVs are annular. Once the lower metal/dielectric stack is formed (including the via dielectric for the metal layer that contacts the TSVs), the TSVs are drilled through to the silicon, and then a Bosch etch is used to drill the vias about 100μm into the substrate, with a minimum pitch of 50μm.

After drilling, a conformal oxide is deposited, the barrier and seed layers are sputtered in, the copper fill is plated in, and any excess copper is CMP'd off. The dielectric for the contact level metal is put down, and then the top fat-wire metal levels are conventionally defined.

Fig.1: SEM cross-section image of annular TSV integrated into M10 level in 45nm technology.


Fig. 1 above shows the TSV contacting the metal 10 level in a 12-metal part. If we guesstimate that M10 is ~1μm thick, that gives us a TSV diameter of about 15μm (which agrees with a verbal comment at the presentation), and the annular copper ring is 4-5μm thick.

Fig.2: Cross-section of TSV bottom, showing Bosch-etch striations and fully-filled via.


It appears by the time M3 is complete, there's about 250μm of bow in the wafer, which continues and will likely get worse by the end of wafer fab. That makes it difficult to bond the wafer flat for thinning, so at the via-2 and via-3 levels compressive oxide is used which pulls the wafer flat again -- see Fig. 3 below.

Fig.3: Wafer bow vs. metal step and change with high-stress oxide at via-2 and via-3 levels.


That will mean that if TSVs are to be used there will have to be a discrete process module within the BEOL, and also the M2/M3 levels will have to be laid out to compensate for dense oxide rather than low-k in processes at 90nm nodes and below. Another cost adder for TSVs!

The completed wafers were bonded to glass handle wafers and thinned to expose the copper at the bottom of the TSVs, after which a protective oxide/nitride was deposited and patterned before forming and defining a copper redistribution layer (RDL). Lead-free C4 solder balls were then put on the the RDL, and the thinned TSV wafer was ready for joining to another die or substrate. After dicing the dies can be bonded with the RDL side on a package substrate with the device side face-to-face with another die, or face down with another die flip-chipped on to the RDL.

Fig. 4 shows a module in which a thin TSV wafer has been packaged RDL-down and another full-thickness die face-to-face with the thinned die.

Fig.4: Module containing thinned TSV die stacked face-to-face with full thickness die.


Test devices were subjected to considerable thermal and reliability testing without adverse effects. The TSV etch process was shown to affect nearby PFETs under certain conditions, but was optimized to solve the problem. The stress associated with the vias was not significant and not expected to create any mobility effects in nearby transistors.

As another test of the TSV process, a 32nm SOI 3D embedded memory module was fabricated with a 128Mb DRAM stacked on top of a 96Mb general purpose DRAM; both with 0.039m² eDRAM cells in high-k/metal gate technology. The memories were tested with no performance or retention degradations observed.

I've no idea when we'll see a real memory cube in production; no dates were given in the announcement, but hopefully sometime next year. Whether we'll be able to get hold of one is another matter!

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