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Monday, November 21, 2011

Intel clarifies 32nm NMOS stress mechanism at IEDM 2011

I was browsing through the advance program for the upcoming IEDM conference when, almost at the end, I came across paper number 34.4, "Modeling of NMOS Performance Gains from Edge Dislocation Stress," by Weber et al. of Intel. According to the abstract: "Simulations show stress from edge dislocations introduced by solid phase epitaxial regrowth increases as gate pitch is scaled, reaching over 1GPa. This makes edge dislocations attractive, as stress from epitaxial and deposited film stressors reduces as pitch is scaled. We show dislocation stress varies with layout and topography."

The abstract doesn't have much detail, but it does re-enforce the teachings from a Samsung paper at last year's IEDM conference, paper 10.1, "Novel Stress-Memorization-Technology (SMT) for High Electron Mobility Enhancement of Gate Last High-k/Metal Gate Devices" (Lim et al.).

The essence of this paper is that if you give the source/drains a deep amorphization implant, and then anneal to create solid-phase epitaxial re-growth with a tensile stress liner in place, then crystalline dislocations are formed adjacent to the gate edge, which apply tensile stress to the channel.

Source: IEDM/Samsung

Like the embedded SiGe stress for PMOS, this works better with a gate-last process, since the surface is not locked by a polysilicon gate. Samsung claimed ~1% lattice distortion, verified by nano-beam diffraction measurements. A vertical slice was taken below the center of the gate and the color coding shows strain of ~1%:

Source: IEDM/Samsung

When I saw this paper it made me wonder if this mechanism was what we had been seeing in the Intel 32nm parts; none of the earlier stress mechanisms seemed to being used. Intel were the first to apply stress to transistor channels at the 90nm node, using (for NMOS) the contact etch-stop layer (CESL) silicon nitride; and then at the 45nm node they evolved to using the contact plug itself and the gate-fill metal, since the CESL is almost gone.

But in the 32nm process the contact plugs have been polished away, and there is less gate metal (since it's a smaller gate) -- so what is supplying Intel's fourth-generation strain?

In the light of these two papers we can now take a good guess when we see what Intel's 32nm NMOS transistor looks like:

And as we can see, there are stacking faults on both sides of the gate, and they look similar to the ones in the image from the Samsung paper:

Source: IEDM/Samsung

Samsung claimed an increase in electron mobility of 40%-60% and drive current improvement of over 10%.

Stacking faults are not normally what we want to see in transistors, because they can be leaky if they go through a junction, but as long as they are contained within the source/drain diffusions, they should not be a problem. They are certainly in every NMOS transistor that we imaged (though given the billions of transistors in the millions of processors shipped, we cannot exactly claim a large sample).

At an intuitive level it makes sense that this mechanism should work -- a stacking fault is a missing layer of atoms within the crystalline lattice, and we are now working with channel lengths of a hundred atomic spacings or less. So if a couple of atomic layers are missing at opposing ends of the channel, it seems logical that tensile stress would be induced in the channel.

Like the other stress techniques, this only works now that we are down in the nanometer range, but the good thing about this one is that the applied strain should increase as the channel length gets shorter.

So it seems that we have finally deduced at least some of what Intel are doing in their 32nm NMOS transistors. Now, of course, the question will be -- can it be transferred to the trigate structures we're looking forward to in the 22nm process?

Looking forward to IEDM, in addition to the conference program, ASM will be holding a lunchtime seminar on the Wednesday, Dec. 7th, at 12 noon, with Ivo Raaijmakers hosting; and I have the privilege of speaking on "High-k/Metal Gate in Leading-Edge Silicon Devices." To register, email Roseanne de Vries at We hope to see you there!

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