As the name says, ASMC is an annual conference focused on the manufacturing of semiconductor devices; in this it differs from other conferences, since the emphasis is on what goes on in the wafer fab, not the R&D labs, and the papers are not research papers. After all, it’s the nitty-gritty of manufacturing in the fab that gets the chips out of the door, and this meeting discusses the work that pushes the yield and volumes up and keeps them there.
I always come away impressed by the quality of the engineering involved; not being a fab person myself any more, it’s easy to get disconnected from the density of effort required to equip a fab, keep it running and bring new products/processes into production. Usually the guys in the fab only get publicity if something goes wrong!
There were 81 papers spread over the three days, with keynotes from Subi Kengeri of GLOBALFOUNDRIES, Vivek Singh and Tim Hendry of Intel, and Bill McClean of IC Insights, and also a panel discussion on the benefits/pitfalls of 450mm wafers. This latter is particularly apposite here in Saratoga Springs since we have the Global 450 Consortium building their new fab at CNSE in Albany, just down the road from here.
The conference kicked off with Subi Kengeri’s keynote – “Assessing the Threats to Semiconductor Growth: Technology Limitations versus Economic Realities” – essentially, will Moore’s law run out of steam before or after chips get too expensive to sell?
|Subi Kengeri of GLOBALFDOUNDRIES giving the opening keynote at ASMC|
And we know that technologically we can get to 14nm or even 10nm with multiple patterning, finFETs, etc., and possibly new materials.
On the other hand, SoC designs are getting larger, faster, and more complex, and wafer fab costs are going up, with lithography being the biggest component. (It’s worth noting here that at the 20nm generation, the middle-of line (MOL) processing separates from the back-end of line (BEOL), since the 1X interconnect level has to be double-patterned.)
This increased design and fab complexity also adds to development time and increases the time-to-volume (TTV), adding a time cost and reducing the return on investment. This could conceivably get the industry into a feedback loop, since TTV delay slows down industry growth, which slows downs investment, which slows down development, which slows down TTV.
The other obvious effect is the industry consolidation which we’ve all been part of – according to Subi only four companies will be fabbing at the 14nm node:
I had wondered why IBM wasn’t on the list until I saw the 50K wafers/month cut-off; even with all the games chips that IBM has churned out over the last few years, I doubt that IBM has hit that number.
If the predictions are correct, by 2016 28nm and below will make up 60 percent of the foundry market, split between four companies (or three, if Intel’s foundry ambitions don’t work out). That thought raised the prospect of capacity limitations, and gave Subi a chance to promote GLOBALFOUNDRIES as the only one of the three with a global footprint, and not in geographically or politically risky zones.
He finished his talk by identifying critical growth enablers for the industry as optimized SoC technology architecture (with a focus on techno-economics), coupled with true collaborative R&D, and of course the global footprint. And he also asked all of us in the room which was the biggest threat to growth – technology scaling limits, or the economic realities? Being techies, we all know that the next few generations are within sight technically, so we all voted for the economic problems – the part we can’t control!
|The final vote|
N.B. All images courtesy of GLOBALFOUNDRIES.