It took us a while to track down a couple of laptops with the requisite Haswell version, but we did and now we have a few images that show it’s a very different structure from the other e-DRAMs that we’ve seen.
IBM has been using e-DRAM for years, and in all of their products since the 45-nm node. They have progressed their trench DRAM technology to the 22-nm node , though we have yet to see that in production.
|Embedded DRAM in IBM Power 7+ (32-nm)|
|Embedded DRAM in Microsoft Xbox GPU fabbed by TSMC (65-nm)|
|Embedded DRAM in Nintendo Wii U GPU fabbed by Renesas (45-nm)|
|General structure of Intel’s 22-nm embedded DRAM part from Haswell package|
|Intel’s 22-nm embedded DRAM stack|
|A closer look at the Intel 22-nm embedded DRAM stack|
|Plan-view image of the Intel 22-nm embedded DRAM capacitors|
Intel claims a cell capacitance of more than 13 fF and a cell size of 0.029 sq. microns, so about a third of their 22-nm SRAM cell area of ~0.09 sq. microns, and a little larger than the IBM equivalent of 0.026 sq. microns. The wordline transistors are low-leakage trigate transistors with an enlarged contacted gate pitch of 108 nm (the minimum CGP is 90 nm).
In the Haswell usage the die is used as a 128 MB L4 cache, with a die size of ~79 sq. mm, co-packaged with the CPU.
|Intel Haswell CPU with co-packaged eDRAM|
 R. Brain et al., A 22nm High Performance Embedded DRAM SoC Technology Featuring Tri-gate Transistors and MIMCAP COB, Proc VLSI Symp 2013, pp. 16-17.
 Y. Wang et al., Retention Time Optimization for eDRAM in 22nm Tri-Gate CMOS Technology, Proc IEDM 2013, pp. 240-243.
 S. Narasimha et al., 22nm High-Performance SOI Technology Featuring Dual-Embedded Stressors, Epi-Plate High-K Deep-Trench Embedded DRAM and Self-Aligned Via 15LM BEOL, Proc. IEDM 2012 pp. 52-55.